Lines Matching refs:sdram_params
390 struct rv1126_sdram_params *sdram_params) in rkclk_configure_ddr() argument
393 rkclk_set_dpll(dram, sdram_params->base.ddr_freq * MHZ / 2); in rkclk_configure_ddr()
397 calculate_ddrconfig(struct rv1126_sdram_params *sdram_params) in calculate_ddrconfig() argument
399 struct sdram_cap_info *cap_info = &sdram_params->ch.cap_info; in calculate_ddrconfig()
415 if (sdram_params->base.dramtype == DDR4) { in calculate_ddrconfig()
486 if (sdram_params->base.dramtype == DDR4) { in calculate_ddrconfig()
524 struct rv1126_sdram_params *sdram_params) in set_ctl_address_map() argument
526 struct sdram_cap_info *cap_info = &sdram_params->ch.cap_info; in set_ctl_address_map()
532 if (sdram_params->base.dramtype == DDR4) { in set_ctl_address_map()
555 if (sdram_params->base.dramtype == LPDDR3 && cap_info->row_3_4) in set_ctl_address_map()
557 if (sdram_params->base.dramtype == DDR4 && cap_info->bw == 0x1) in set_ctl_address_map()
884 struct rv1126_sdram_params *sdram_params, u32 dst_fsp) in set_ds_odt() argument
888 u32 dramtype = sdram_params->base.dramtype; in set_ds_odt()
900 u32 freq = sdram_params->base.ddr_freq; in set_ds_odt()
1225 struct rv1126_sdram_params *sdram_params) in sdram_cmd_dq_path_remap() argument
1228 u32 dramtype = sdram_params->base.dramtype; in sdram_cmd_dq_path_remap()
1248 struct rv1126_sdram_params *sdram_params) in phy_cfg() argument
1250 struct sdram_cap_info *cap_info = &sdram_params->ch.cap_info; in phy_cfg()
1255 sdram_cmd_dq_path_remap(dram, sdram_params); in phy_cfg()
1257 phy_pll_set(dram, sdram_params->base.ddr_freq * MHZ, 0); in phy_cfg()
1258 for (i = 0; sdram_params->phy_regs.phy[i][0] != 0xFFFFFFFF; i++) { in phy_cfg()
1259 writel(sdram_params->phy_regs.phy[i][1], in phy_cfg()
1260 phy_base + sdram_params->phy_regs.phy[i][0]); in phy_cfg()
1289 if (sdram_params->base.dramtype == LPDDR4 || in phy_cfg()
1290 sdram_params->base.dramtype == LPDDR4X) in phy_cfg()
1940 struct rv1126_sdram_params *sdram_params, u32 dst_fsp, in data_training() argument
1951 sdram_params->base.dramtype, in data_training()
1952 sdram_params->ch.cap_info.rank); in data_training()
1959 sdram_params->base.dramtype); in data_training()
1966 sdram_params->base.dramtype, in data_training()
1967 sdram_params->base.ddr_freq); in data_training()
1974 sdram_params->base.dramtype, in data_training()
1975 sdram_params->base.ddr_freq, dst_fsp); in data_training()
1985 struct rv1126_sdram_params *sdram_params) in get_wrlvl_val() argument
1996 sdram_params->base.dramtype); in get_wrlvl_val()
1998 ret = data_training(dram, 0, sdram_params, 0, WRITE_LEVELING); in get_wrlvl_val()
1999 if (sdram_params->ch.cap_info.rank == 2) in get_wrlvl_val()
2000 ret |= data_training(dram, 1, sdram_params, 0, WRITE_LEVELING); in get_wrlvl_val()
2099 struct rv1126_sdram_params *sdram_params, in high_freq_training() argument
2104 u32 dramtype = sdram_params->base.dramtype; in high_freq_training()
2112 for (j = 0; j < sdram_params->ch.cap_info.rank; j++) { in high_freq_training()
2119 (int)(sdram_params->ch.cap_info.rank * (1 << sdram_params->ch.cap_info.bw)); in high_freq_training()
2126 for (j = 0; j < sdram_params->ch.cap_info.rank; j++) in high_freq_training()
2151 ret = data_training(dram, 0, sdram_params, fsp, READ_GATE_TRAINING | in high_freq_training()
2154 rw_trn_result.fsp_mhz[fsp] = (u16)sdram_params->base.ddr_freq; in high_freq_training()
2159 if (sdram_params->ch.cap_info.rank == 2) { in high_freq_training()
2164 ret |= data_training(dram, 1, sdram_params, fsp, in high_freq_training()
2179 sdram_params->ch.cap_info.rank) * -1; in high_freq_training()
2181 min_val, min_val, sdram_params->ch.cap_info.rank); in high_freq_training()
2189 sdram_params->ch.cap_info.rank), in high_freq_training()
2191 sdram_params->ch.cap_info.rank)) * -1; in high_freq_training()
2198 min_val, min_val, sdram_params->ch.cap_info.rank); in high_freq_training()
2205 ret = data_training(dram, 0, sdram_params, 0, READ_GATE_TRAINING); in high_freq_training()
2206 if (sdram_params->ch.cap_info.rank == 2) in high_freq_training()
2207 ret |= data_training(dram, 1, sdram_params, 0, in high_freq_training()
2220 struct rv1126_sdram_params *sdram_params) in update_noc_timing() argument
2225 bw = 8 << sdram_params->ch.cap_info.bw; in update_noc_timing()
2230 sdram_params->ch.noc_timings.ddrmode.b.burstsize = 0; in update_noc_timing()
2232 sdram_params->ch.noc_timings.ddrmode.b.burstsize = 1; in update_noc_timing()
2234 sdram_params->ch.noc_timings.ddrmode.b.burstsize = 2; in update_noc_timing()
2236 sdram_params->ch.noc_timings.ddrmode.b.burstsize = 3; in update_noc_timing()
2238 sdram_params->ch.noc_timings.ddrtimingc0.b.burstpenalty = in update_noc_timing()
2241 if (sdram_params->base.dramtype == LPDDR4 || in update_noc_timing()
2242 sdram_params->base.dramtype == LPDDR4X) { in update_noc_timing()
2243 sdram_params->ch.noc_timings.ddrmode.b.mwrsize = in update_noc_timing()
2245 sdram_params->ch.noc_timings.ddrtimingc0.b.wrtomwr = in update_noc_timing()
2246 3 * sdram_params->ch.noc_timings.ddrtimingc0.b.burstpenalty; in update_noc_timing()
2249 writel(sdram_params->ch.noc_timings.ddrtiminga0.d32, in update_noc_timing()
2251 writel(sdram_params->ch.noc_timings.ddrtimingb0.d32, in update_noc_timing()
2253 writel(sdram_params->ch.noc_timings.ddrtimingc0.d32, in update_noc_timing()
2255 writel(sdram_params->ch.noc_timings.devtodev0.d32, in update_noc_timing()
2257 writel(sdram_params->ch.noc_timings.ddrmode.d32, &dram->msch->ddrmode); in update_noc_timing()
2258 writel(sdram_params->ch.noc_timings.ddr4timing.d32, in update_noc_timing()
2263 struct rv1126_sdram_params *sdram_params) in split_setup() argument
2265 struct sdram_cap_info *cap_info = &sdram_params->ch.cap_info; in split_setup()
2266 u32 dramtype = sdram_params->base.dramtype; in split_setup()
2328 struct rv1126_sdram_params *sdram_params) in dram_all_config() argument
2330 struct sdram_cap_info *cap_info = &sdram_params->ch.cap_info; in dram_all_config()
2331 u32 dram_type = sdram_params->base.dramtype; in dram_all_config()
2339 sdram_org_config(cap_info, &sdram_params->base, &sys_reg2, in dram_all_config()
2357 update_noc_timing(dram, sdram_params); in dram_all_config()
2361 struct rv1126_sdram_params *sdram_params) in enable_low_power() argument
2368 if (sdram_params->base.dramtype == DDR4) in enable_low_power()
2370 else if (sdram_params->base.dramtype == DDR3) in enable_low_power()
2392 struct rv1126_sdram_params *sdram_params) in ddr_set_atags() argument
2394 struct sdram_cap_info *cap_info = &sdram_params->ch.cap_info; in ddr_set_atags()
2395 u32 dram_type = sdram_params->base.dramtype; in ddr_set_atags()
2455 static void print_ddr_info(struct rv1126_sdram_params *sdram_params) in print_ddr_info() argument
2466 sdram_print_ddr_info(&sdram_params->ch.cap_info, in print_ddr_info()
2467 &sdram_params->base, split); in print_ddr_info()
2490 static int check_lp4_rzqi(struct dram_info *dram, struct rv1126_sdram_params *sdram_params) in check_lp4_rzqi() argument
2493 u32 dramtype = sdram_params->base.dramtype; in check_lp4_rzqi()
2500 cap_info = &sdram_params->ch.cap_info; in check_lp4_rzqi()
2518 int modify_ddr34_bw_byte_map(u8 rg_result, struct rv1126_sdram_params *sdram_params) in modify_ddr34_bw_byte_map() argument
2523 struct sdram_cap_info *cap_info = &sdram_params->ch.cap_info; in modify_ddr34_bw_byte_map()
2524 u32 dramtype = sdram_params->base.dramtype; in modify_ddr34_bw_byte_map()
2560 pctl_remodify_sdram_params(&sdram_params->pctl_regs, cap_info, dramtype); in modify_ddr34_bw_byte_map()
2567 int sdram_init_(struct dram_info *dram, struct rv1126_sdram_params *sdram_params, u32 post_init) in sdram_init_() argument
2575 rkclk_configure_ddr(dram, sdram_params); in sdram_init_()
2581 phy_cfg(dram, sdram_params); in sdram_init_()
2584 phy_pll_set(dram, sdram_params->base.ddr_freq * MHZ, 1); in sdram_init_()
2587 pctl_cfg(dram->pctl, &sdram_params->pctl_regs, in sdram_init_()
2590 if (sdram_params->ch.cap_info.bw == 2) { in sdram_init_()
2613 set_ds_odt(dram, sdram_params, 0); in sdram_init_()
2614 sdram_params->ch.cap_info.ddrconfig = calculate_ddrconfig(sdram_params); in sdram_init_()
2615 set_ctl_address_map(dram, sdram_params); in sdram_init_()
2630 if (sdram_params->base.dramtype == LPDDR3) { in sdram_init_()
2632 } else if (sdram_params->base.dramtype == LPDDR4 || in sdram_init_()
2633 sdram_params->base.dramtype == LPDDR4X) { in sdram_init_()
2649 } else if (sdram_params->base.dramtype == DDR4) { in sdram_init_()
2656 if (sdram_params->base.dramtype == DDR3 && post_init == 0) in sdram_init_()
2658 tmp = data_training(dram, 0, sdram_params, 0, READ_GATE_TRAINING) & 0xf; in sdram_init_()
2665 if (sdram_params->base.dramtype != DDR3 || tmp == 0xf) in sdram_init_()
2669 if (sdram_params->base.dramtype == DDR3 && post_init == 0) { in sdram_init_()
2670 if (modify_ddr34_bw_byte_map((u8)tmp, sdram_params) != 0) in sdram_init_()
2674 if (sdram_params->base.dramtype == LPDDR4) { in sdram_init_()
2681 if (sdram_params->base.dramtype == LPDDR4 || in sdram_init_()
2682 sdram_params->base.dramtype == LPDDR4X) { in sdram_init_()
2689 if (post_init != 0 && sdram_params->ch.cap_info.rank == 2) { in sdram_init_()
2690 if (data_training(dram, 1, sdram_params, 0, in sdram_init_()
2697 if (sdram_params->base.dramtype == DDR4) { in sdram_init_()
2700 sdram_params->base.dramtype); in sdram_init_()
2703 dram_all_config(dram, sdram_params); in sdram_init_()
2704 enable_low_power(dram, sdram_params); in sdram_init_()
2710 struct rv1126_sdram_params *sdram_params, in dram_detect_cap() argument
2713 struct sdram_cap_info *cap_info = &sdram_params->ch.cap_info; in dram_detect_cap()
2722 u32 dram_type = sdram_params->base.dramtype; in dram_detect_cap()
2788 if (data_training(dram, 1, sdram_params, 0, READ_GATE_TRAINING) == 0) in dram_detect_cap()
2809 if (data_training(dram, 0, sdram_params, 0, READ_GATE_TRAINING) == 0) in dram_detect_cap()
2836 struct rv1126_sdram_params *sdram_params, in dram_detect_cs1_row() argument
2839 struct sdram_cap_info *cap_info = &sdram_params->ch.cap_info; in dram_detect_cs1_row()
2858 if (sdram_params->base.dramtype == DDR4) { in dram_detect_cs1_row()
2905 struct rv1126_sdram_params *sdram_params) in sdram_init_detect() argument
2907 struct sdram_cap_info *cap_info = &sdram_params->ch.cap_info; in sdram_init_detect()
2912 if (sdram_init_(dram, sdram_params, 0)) { in sdram_init_detect()
2913 if (sdram_params->base.dramtype == DDR3) { in sdram_init_detect()
2914 if (sdram_init_(dram, sdram_params, 0)) in sdram_init_detect()
2921 if (sdram_params->base.dramtype == DDR3) { in sdram_init_detect()
2928 if (dram_detect_cap(dram, sdram_params, 0) != 0) in sdram_init_detect()
2931 pctl_remodify_sdram_params(&sdram_params->pctl_regs, cap_info, in sdram_init_detect()
2932 sdram_params->base.dramtype); in sdram_init_detect()
2933 ret = sdram_init_(dram, sdram_params, 1); in sdram_init_detect()
2938 dram_detect_cs1_row(dram, sdram_params, 0); in sdram_init_detect()
2948 sdram_detect_high_row(cap_info, sdram_params->base.dramtype); in sdram_init_detect()
2949 split_setup(dram, sdram_params); in sdram_init_detect()
3011 struct rv1126_sdram_params *sdram_params, in pre_set_rate() argument
3019 u32 dramtype = sdram_params->base.dramtype; in pre_set_rate()
3024 for (j = find; sdram_params->pctl_regs.pctl[j][0] != 0xFFFFFFFF; in pre_set_rate()
3026 if (sdram_params->pctl_regs.pctl[j][0] == in pre_set_rate()
3028 writel(sdram_params->pctl_regs.pctl[j][1], in pre_set_rate()
3055 for (j = find; sdram_params->phy_regs.phy[j][0] != 0xFFFFFFFF; in pre_set_rate()
3057 if (sdram_params->phy_regs.phy[j][0] == in pre_set_rate()
3059 writel(sdram_params->phy_regs.phy[j][1], in pre_set_rate()
3068 set_ds_odt(dram, sdram_params, dst_fsp); in pre_set_rate()
3133 update_noc_timing(dram, sdram_params); in pre_set_rate()
3137 struct rv1126_sdram_params *sdram_params) in save_fsp_param() argument
3145 ddr_info = get_ddr_drv_odt_info(sdram_params->base.dramtype); in save_fsp_param()
3147 p_fsp_param->freq_mhz = sdram_params->base.ddr_freq; in save_fsp_param()
3149 if (sdram_params->base.dramtype == LPDDR4 || in save_fsp_param()
3150 sdram_params->base.dramtype == LPDDR4X) { in save_fsp_param()
3172 if (sdram_params->base.dramtype == DDR3) { in save_fsp_param()
3179 } else if (sdram_params->base.dramtype == DDR4) { in save_fsp_param()
3186 } else if (sdram_params->base.dramtype == LPDDR3) { in save_fsp_param()
3194 } else if (sdram_params->base.dramtype == LPDDR4 || in save_fsp_param()
3195 sdram_params->base.dramtype == LPDDR4X) { in save_fsp_param()
3227 sdram_params->ch.noc_timings.ddrtiminga0; in save_fsp_param()
3229 sdram_params->ch.noc_timings.ddrtimingb0; in save_fsp_param()
3231 sdram_params->ch.noc_timings.ddrtimingc0; in save_fsp_param()
3233 sdram_params->ch.noc_timings.devtodev0; in save_fsp_param()
3235 sdram_params->ch.noc_timings.ddrmode; in save_fsp_param()
3237 sdram_params->ch.noc_timings.ddr4timing; in save_fsp_param()
3239 sdram_params->ch.noc_timings.agingx0; in save_fsp_param()
3241 sdram_params->ch.noc_timings.aging0; in save_fsp_param()
3243 sdram_params->ch.noc_timings.aging1; in save_fsp_param()
3245 sdram_params->ch.noc_timings.aging2; in save_fsp_param()
3247 sdram_params->ch.noc_timings.aging3; in save_fsp_param()
3381 struct rv1126_sdram_params *sdram_params, in ddr_set_rate() argument
3388 u32 dramtype = sdram_params->base.dramtype; in ddr_set_rate()
3396 sdram_params_new->ch.cap_info.rank = sdram_params->ch.cap_info.rank; in ddr_set_rate()
3397 sdram_params_new->ch.cap_info.bw = sdram_params->ch.cap_info.bw; in ddr_set_rate()
3400 &sdram_params->ch.cap_info, dramtype, freq); in ddr_set_rate()
3578 struct rv1126_sdram_params *sdram_params) in ddr_set_rate_for_fsp() argument
3582 u32 dramtype = sdram_params->base.dramtype; in ddr_set_rate_for_fsp()
3606 if (get_wrlvl_val(dram, sdram_params)) in ddr_set_rate_for_fsp()
3613 ddr_set_rate(&dram_info, sdram_params, f1, in ddr_set_rate_for_fsp()
3614 sdram_params->base.ddr_freq, 1, 1, 1); in ddr_set_rate_for_fsp()
3618 ddr_set_rate(&dram_info, sdram_params, f2, f1, 2, 0, 1); in ddr_set_rate_for_fsp()
3622 ddr_set_rate(&dram_info, sdram_params, f3, f2, 3, 1, 1); in ddr_set_rate_for_fsp()
3628 ddr_set_rate(&dram_info, sdram_params, f0, f3, 0, 0, 1); in ddr_set_rate_for_fsp()
3630 ddr_set_rate(&dram_info, sdram_params, f0, sdram_params->base.ddr_freq, 1, 1, 1); in ddr_set_rate_for_fsp()
3649 struct rv1126_sdram_params *sdram_params; in sdram_init() local
3692 sdram_params = &sdram_configs[0]; in sdram_init()
3697 if (sdram_params->base.dramtype == DDR3 || in sdram_init()
3698 sdram_params->base.dramtype == DDR4) { in sdram_init()
3700 sdram_params->pctl_regs.pctl[0][1] |= 0x1 << 10; in sdram_init()
3702 sdram_params->pctl_regs.pctl[0][1] &= in sdram_init()
3705 ret = sdram_init_detect(&dram_info, sdram_params); in sdram_init()
3707 sdram_print_dram_type(sdram_params->base.dramtype); in sdram_init()
3709 printdec(sdram_params->base.ddr_freq); in sdram_init()
3713 print_ddr_info(sdram_params); in sdram_init()
3715 if (check_lp4_rzqi(&dram_info, sdram_params)) in sdram_init()
3721 (u8)sdram_params->ch.cap_info.rank); in sdram_init()
3724 ddr_set_rate_for_fsp(&dram_info, sdram_params); in sdram_init()
3729 ddr_set_atags(&dram_info, sdram_params); in sdram_init()