1835 	u32 mr_tmp, cl, cwl, phy_fsp, offset = 0;  in data_training_wr()  local
1930 		mr_tmp = readl(pctl_base + UMCTL2_REGS_FREQ(cur_fsp) +  in data_training_wr()
1932 		pctl_write_mr(dram->pctl, 3, 2, mr_tmp & PCTL2_MR_MASK,  in data_training_wr()
2572 	u32 mr_tmp, tmp;  in sdram_init_()  local
2634 		mr_tmp = readl(pctl_base + DDR_PCTL2_INIT6);  in sdram_init_()
2637 			      mr_tmp >> PCTL2_LPDDR4_MR11_SHIFT & PCTL2_MR_MASK,  in sdram_init_()
2641 			      mr_tmp >> PCTL2_LPDDR4_MR12_SHIFT & PCTL2_MR_MASK,  in sdram_init_()
2644 		mr_tmp = readl(pctl_base + DDR_PCTL2_INIT7);  in sdram_init_()
2647 			      mr_tmp >> PCTL2_LPDDR4_MR22_SHIFT & PCTL2_MR_MASK,  in sdram_init_()
2650 		mr_tmp = readl(pctl_base + DDR_PCTL2_INIT7) >> PCTL2_DDR4_MR6_SHIFT & PCTL2_MR_MASK;  in sdram_init_()
2651 		pctl_write_mr(dram->pctl, 0x3, 6, mr_tmp | BIT(7), DDR4);  in sdram_init_()
2652 		pctl_write_mr(dram->pctl, 0x3, 6, mr_tmp | BIT(7), DDR4);  in sdram_init_()
2653 		pctl_write_mr(dram->pctl, 0x3, 6, mr_tmp, DDR4);  in sdram_init_()
2675 		mr_tmp = read_mr(dram, 1, 0, 14, LPDDR4);  in sdram_init_()
2677 		if (mr_tmp != 0x4d)  in sdram_init_()
2683 		mr_tmp = readl(pctl_base + DDR_PCTL2_INIT7);  in sdram_init_()
2686 			      mr_tmp >> PCTL2_LPDDR4_MR14_SHIFT & PCTL2_MR_MASK,  in sdram_init_()
3018 	u32 mr_tmp;  in pre_set_rate()  local
3070 		mr_tmp = readl(pctl_base + UMCTL2_REGS_FREQ(dst_fsp) +  in pre_set_rate()
3074 			      ((mr_tmp >> PCTL2_LPDDR4_MR13_SHIFT &  in pre_set_rate()
3077 		writel(((mr_tmp >> PCTL2_LPDDR4_MR13_SHIFT &  in pre_set_rate()
3083 			      mr_tmp >> PCTL2_LPDDR234_MR3_SHIFT &  in pre_set_rate()
3086 		writel(mr_tmp >> PCTL2_LPDDR234_MR3_SHIFT & PCTL2_MR_MASK,  in pre_set_rate()
3089 		mr_tmp = readl(pctl_base + UMCTL2_REGS_FREQ(dst_fsp) +  in pre_set_rate()
3093 			      mr_tmp >> PCTL2_LPDDR234_MR1_SHIFT &  in pre_set_rate()
3096 		writel(mr_tmp >> PCTL2_LPDDR234_MR1_SHIFT & PCTL2_MR_MASK,  in pre_set_rate()
3099 		pctl_write_mr(dram->pctl, 3, 2, mr_tmp & PCTL2_MR_MASK,  in pre_set_rate()
3101 		writel(mr_tmp & PCTL2_MR_MASK,  in pre_set_rate()
3104 		mr_tmp = readl(pctl_base + UMCTL2_REGS_FREQ(dst_fsp) +  in pre_set_rate()
3108 			      mr_tmp >> PCTL2_LPDDR4_MR11_SHIFT & PCTL2_MR_MASK,  in pre_set_rate()
3110 		writel(mr_tmp >> PCTL2_LPDDR4_MR11_SHIFT & PCTL2_MR_MASK,  in pre_set_rate()
3114 			      mr_tmp >> PCTL2_LPDDR4_MR12_SHIFT & PCTL2_MR_MASK,  in pre_set_rate()
3117 		mr_tmp = readl(pctl_base + UMCTL2_REGS_FREQ(dst_fsp) +  in pre_set_rate()
3121 			      mr_tmp >> PCTL2_LPDDR4_MR22_SHIFT & PCTL2_MR_MASK,  in pre_set_rate()
3123 		writel(mr_tmp >> PCTL2_LPDDR4_MR22_SHIFT & PCTL2_MR_MASK,  in pre_set_rate()
3127 			      mr_tmp >> PCTL2_LPDDR4_MR14_SHIFT & PCTL2_MR_MASK,  in pre_set_rate()
3129 		writel(mr_tmp >> PCTL2_LPDDR4_MR14_SHIFT & PCTL2_MR_MASK,  in pre_set_rate()
3386 	u32 mr_tmp;  in ddr_set_rate()  local
3502 	mr_tmp = readl(pctl_base + UMCTL2_REGS_FREQ(dst_fsp) + DDR_PCTL2_INIT4);  in ddr_set_rate()
3511 			      (mr_tmp >> PCTL2_LPDDR234_MR3_SHIFT) &  in ddr_set_rate()
3530 			      ((mr_tmp >> PCTL2_DDR34_MR2_SHIFT) &  in ddr_set_rate()
3533 			pctl_write_mr(dram->pctl, 3, 3, mr_tmp & PCTL2_MR_MASK,  in ddr_set_rate()
3535 			mr_tmp = readl(pctl_base + UMCTL2_REGS_FREQ(dst_fsp) +  in ddr_set_rate()
3538 				      (mr_tmp >> PCTL2_DDR4_MR4_SHIFT) &  in ddr_set_rate()
3542 				      mr_tmp >> PCTL2_DDR4_MR5_SHIFT &  in ddr_set_rate()
3546 			mr_tmp = readl(pctl_base + UMCTL2_REGS_FREQ(dst_fsp) +  in ddr_set_rate()
3550 				      (mr_tmp | (0x1 << 7)) >> PCTL2_DDR4_MR6_SHIFT &  in ddr_set_rate()
3553 				      (mr_tmp | (0x1 << 7)) >> PCTL2_DDR4_MR6_SHIFT &  in ddr_set_rate()
3556 				      mr_tmp >> PCTL2_DDR4_MR6_SHIFT &  in ddr_set_rate()
3562 			      ((mr_tmp >> PCTL2_LPDDR4_MR13_SHIFT &  in ddr_set_rate()