364 		clrsetbits_le32(&dram->cru->pll[1].con2,  in rkclk_set_dpll()
561 		clrsetbits_le32(pctl_base + DDR_PCTL2_ADDRMAP0, 0x1f, 0x1f);  in set_ctl_address_map()
597 		clrsetbits_le32(PHY_REG(phy_base, 0x51), PHY_PBDIV_BIT9_MASK,  in phy_pll_set()
599 		clrsetbits_le32(PHY_REG(phy_base, 0x51), PHY_POSTDIV_EN_MASK,  in phy_pll_set()
602 		clrsetbits_le32(PHY_REG(phy_base, 0x52),  in phy_pll_set()
604 		clrsetbits_le32(PHY_REG(phy_base, 0x53),  in phy_pll_set()
871 	clrsetbits_le32(pctl_base + UMCTL2_REGS_FREQ(dst_fsp) +  in set_lp4_vref()
876 	clrsetbits_le32(pctl_base + UMCTL2_REGS_FREQ(dst_fsp) +  in set_lp4_vref()
1043 	clrsetbits_le32(PHY_REG(phy_base, 0x100), 0x1f, phy_ca_drv);  in set_ds_odt()
1044 	clrsetbits_le32(PHY_REG(phy_base, 0x101), 0x1f, phy_ca_drv);  in set_ds_odt()
1045 	clrsetbits_le32(PHY_REG(phy_base, 0x102), 0x1f, phy_clk_drv);  in set_ds_odt()
1046 	clrsetbits_le32(PHY_REG(phy_base, 0x103), 0x1f, phy_clk_drv);  in set_ds_odt()
1048 		clrsetbits_le32(PHY_REG(phy_base, 0x107), 0x1f, phy_clk_drv);  in set_ds_odt()
1049 		clrsetbits_le32(PHY_REG(phy_base, 0x108), 0x1f, phy_clk_drv);  in set_ds_odt()
1051 		clrsetbits_le32(PHY_REG(phy_base, 0x107), 0x1f, phy_ca_drv);  in set_ds_odt()
1052 		clrsetbits_le32(PHY_REG(phy_base, 0x108), 0x1f, phy_ca_drv);  in set_ds_odt()
1055 	clrsetbits_le32(PHY_REG(phy_base, 0x106), 0x1f, sr_clk);  in set_ds_odt()
1065 		clrsetbits_le32(PHY_REG(phy_base, j + 1), 0x1f, phy_odt_up);  in set_ds_odt()
1066 		clrsetbits_le32(PHY_REG(phy_base, j), 0x1f, phy_odt_dn);  in set_ds_odt()
1067 		clrsetbits_le32(PHY_REG(phy_base, j + 2), 0x1f, phy_dq_drv);  in set_ds_odt()
1068 		clrsetbits_le32(PHY_REG(phy_base, j + 3), 0x1f, phy_dq_drv);  in set_ds_odt()
1071 		clrsetbits_le32(PHY_REG(phy_base, 0x114 + i * 0x10),  in set_ds_odt()
1076 		clrsetbits_le32(PHY_REG(phy_base, 0x117 + i * 0x10),  in set_ds_odt()
1177 		clrsetbits_le32(pctl_base + UMCTL2_REGS_FREQ(dst_fsp) +  in set_ds_odt()
1200 		clrsetbits_le32(pctl_base + UMCTL2_REGS_FREQ(dst_fsp) +  in set_ds_odt()
1209 		clrsetbits_le32(pctl_base + UMCTL2_REGS_FREQ(dst_fsp) +  in set_ds_odt()
1216 		clrsetbits_le32(pctl_base + UMCTL2_REGS_FREQ(dst_fsp) +  in set_ds_odt()
1291 		clrsetbits_le32(PHY_REG(phy_base, 0x20), 0x7 << 4,  in phy_cfg()
1397 	clrsetbits_le32(PHY_REG(phy_base, 0x70), BIT(1) | BIT(6) | BIT(4),  in update_dq_rx_prebit()
1611 	clrsetbits_le32(PHY_REG(phy_base, 2), 0x33, (0x20 >> cs));  in data_training_rg()
1613 	clrsetbits_le32(PHY_REG(phy_base, 2), 0x33, (0x20 >> cs) | 1);  in data_training_rg()
1617 	clrsetbits_le32(PHY_REG(phy_base, 2), 0x33, (0x20 >> cs) | 0);  in data_training_rg()
1668 	clrsetbits_le32(PHY_REG(phy_base, 2), (0x3 << 6) | (0x3 << 2),  in data_training_wl()
1671 	clrsetbits_le32(PHY_REG(phy_base, 2), (0x3 << 6) | (0x3 << 2),  in data_training_wl()
1688 	clrsetbits_le32(PHY_REG(phy_base, 2), (0x3 << 6) | (0x3 << 2),  in data_training_wl()
1690 	clrsetbits_le32(PHY_REG(phy_base, 2), 0x3 << 6, 0 << 6);  in data_training_wl()
1752 	clrsetbits_le32(PHY_REG(phy_base, 0x6e), 0xff, trefi_1x & 0xff);  in data_training_rd()
1753 	clrsetbits_le32(PHY_REG(phy_base, 0x6f), 0x3f, (trefi_1x >> 8) & 0x3f);  in data_training_rd()
1755 	clrsetbits_le32(PHY_REG(phy_base, 0x57), 0xff, trfc_1x);  in data_training_rd()
1757 	clrsetbits_le32(PHY_REG(phy_base, 0x61), 0xf << 4, 0x8 << 4);  in data_training_rd()
1760 	clrsetbits_le32(PHY_REG(phy_base, 0x71), 0x3 << 6, (0x2 >> cs) << 6);  in data_training_rd()
1776 	clrsetbits_le32(PHY_REG(phy_base, 0x230), 0x3f, dqs_default);  in data_training_rd()
1778 	clrsetbits_le32(PHY_REG(phy_base, 0x234), 0x3f, dqs_default);  in data_training_rd()
1780 	clrsetbits_le32(PHY_REG(phy_base, 0x2b0), 0x3f, dqs_default);  in data_training_rd()
1782 	clrsetbits_le32(PHY_REG(phy_base, 0x2b4), 0x3f, dqs_default);  in data_training_rd()
1785 	clrsetbits_le32(PHY_REG(phy_base, 0x70), 0x3, 0x1);  in data_training_rd()
1787 	clrsetbits_le32(PHY_REG(phy_base, 0x70), 0x3, 0x3);  in data_training_rd()
1843 		clrsetbits_le32(PHY_REG(phy_base, offset), 0x1f, 0x8);  in data_training_wr()
1844 		clrsetbits_le32(PHY_REG(phy_base, offset + 2), 0x1f, 0x4);  in data_training_wr()
1851 	clrsetbits_le32(PHY_REG(phy_base, 0x7b), 0xff, 0x0);  in data_training_wr()
1853 	clrsetbits_le32(PHY_REG(phy_base, 0x7c), 0x7 << 2, 0x0 << 2);  in data_training_wr()
1855 	clrsetbits_le32(PHY_REG(phy_base, 0x7c), 0x3, 0x0);  in data_training_wr()
1857 	clrsetbits_le32(PHY_REG(phy_base, 0x7d), 0xff, 0x0);  in data_training_wr()
1859 	clrsetbits_le32(PHY_REG(phy_base, 0x7e), 0xff, 0x0);  in data_training_wr()
1871 	clrsetbits_le32(PHY_REG(phy_base, 0x6e), 0xff, trefi_1x & 0xff);  in data_training_wr()
1872 	clrsetbits_le32(PHY_REG(phy_base, 0x6f), 0x3f, (trefi_1x >> 8) & 0x3f);  in data_training_wr()
1874 	clrsetbits_le32(PHY_REG(phy_base, 0x57), 0xff, trfc_1x);  in data_training_wr()
1876 	clrsetbits_le32(PHY_REG(phy_base, 0x61), 0xf << 4, 0x8 << 4);  in data_training_wr()
1879 	clrsetbits_le32(PHY_REG(phy_base, 0x7c), 0x3 << 6, (0x2 >> cs) << 6);  in data_training_wr()
1928 		clrsetbits_le32(PHY_REG(phy_base, offset), 0x1f, cl);  in data_training_wr()
1929 		clrsetbits_le32(PHY_REG(phy_base, offset + 2), 0x1f, cwl);  in data_training_wr()
2216 	clrsetbits_le32(&dram->grf->noc_con0, 0x3 << 0, 0 << 0);  in set_ddrconfig()
2558 		clrsetbits_le32(&map_info->byte_map[0],  in modify_ddr34_bw_byte_map()
2594 		clrsetbits_le32(pctl_base + DDR_PCTL2_SCHED1, 0xff, 0x1 << 0);  in sdram_init_()
2611 	clrsetbits_le32(pctl_base + DDR_PCTL2_MSTR2, 0x3, 0);  in sdram_init_()
2807 			clrsetbits_le32(PHY_REG(phy_base, 0xf), PHY_DQ_WIDTH_MASK,  in dram_detect_cap()
3492 	clrsetbits_le32(pctl_base + DDR_PCTL2_MSTR2, 0x3, dst_fsp);  in ddr_set_rate()
3495 	clrsetbits_le32(PHY_REG(phy_base, 0xc), 0x3 << 2, dst_fsp << 2);  in ddr_set_rate()