399 	struct sdram_cap_info *cap_info = &sdram_params->ch.cap_info;  in calculate_ddrconfig()  local
406 	cs = cap_info->rank;  in calculate_ddrconfig()
407 	bw = cap_info->bw;  in calculate_ddrconfig()
408 	die_bw = cap_info->dbw;  in calculate_ddrconfig()
409 	col = cap_info->col;  in calculate_ddrconfig()
410 	row = cap_info->cs0_row;  in calculate_ddrconfig()
411 	cs1_row = cap_info->cs1_row;  in calculate_ddrconfig()
412 	bank = cap_info->bk;  in calculate_ddrconfig()
413 	row_3_4 = cap_info->row_3_4;  in calculate_ddrconfig()
526 	struct sdram_cap_info *cap_info = &sdram_params->ch.cap_info;  in set_ctl_address_map()  local
528 	u32 ddrconf = cap_info->ddrconfig;  in set_ctl_address_map()
531 	row = cap_info->cs0_row;  in set_ctl_address_map()
555 	if (sdram_params->base.dramtype == LPDDR3 && cap_info->row_3_4)  in set_ctl_address_map()
557 	if (sdram_params->base.dramtype == DDR4 && cap_info->bw == 0x1)  in set_ctl_address_map()
560 	if (cap_info->rank == 1)  in set_ctl_address_map()
1250 	struct sdram_cap_info *cap_info = &sdram_params->ch.cap_info;  in phy_cfg()  local
1279 	if (cap_info->bw == 2)  in phy_cfg()
1281 	else if (cap_info->bw == 1)  in phy_cfg()
1952 				       sdram_params->ch.cap_info.rank);  in data_training()
1999 	if (sdram_params->ch.cap_info.rank == 2)  in get_wrlvl_val()
2112 	for (j = 0; j < sdram_params->ch.cap_info.rank; j++) {  in high_freq_training()
2119 		   (int)(sdram_params->ch.cap_info.rank * (1 << sdram_params->ch.cap_info.bw));  in high_freq_training()
2126 		for (j = 0; j < sdram_params->ch.cap_info.rank; j++)  in high_freq_training()
2159 	if (sdram_params->ch.cap_info.rank == 2) {  in high_freq_training()
2179 				sdram_params->ch.cap_info.rank) * -1;  in high_freq_training()
2181 			 min_val, min_val, sdram_params->ch.cap_info.rank);  in high_freq_training()
2189 				    sdram_params->ch.cap_info.rank),  in high_freq_training()
2191 				    sdram_params->ch.cap_info.rank)) * -1;  in high_freq_training()
2198 			 min_val, min_val, sdram_params->ch.cap_info.rank);  in high_freq_training()
2206 	if (sdram_params->ch.cap_info.rank == 2)  in high_freq_training()
2225 	bw = 8 << sdram_params->ch.cap_info.bw;  in update_noc_timing()
2265 	struct sdram_cap_info *cap_info = &sdram_params->ch.cap_info;  in split_setup()  local
2270 	cs_cap[0] = sdram_get_cs_cap(cap_info, 0, dramtype);  in split_setup()
2271 	cs_cap[1] = sdram_get_cs_cap(cap_info, 1, dramtype);  in split_setup()
2278 	if (cap_info->cs0_high16bit_row < cap_info->cs0_row) {  in split_setup()
2279 		cap = cs_cap[0] / (1 << (cap_info->cs0_row -  in split_setup()
2280 		cap_info->cs0_high16bit_row));  in split_setup()
2281 	} else if ((cap_info->cs1_high16bit_row < cap_info->cs1_row) &&  in split_setup()
2282 		   (cap_info->rank == 2)) {  in split_setup()
2283 		if (!cap_info->cs1_high16bit_row)  in split_setup()
2286 			cap = cs_cap[0] + cs_cap[1] / (1 << (cap_info->cs1_row -  in split_setup()
2287 				cap_info->cs1_high16bit_row));  in split_setup()
2292 	if (cap_info->bw == 2)  in split_setup()
2330 	struct sdram_cap_info *cap_info = &sdram_params->ch.cap_info;  in dram_all_config()  local
2338 	set_ddrconfig(dram, cap_info->ddrconfig);  in dram_all_config()
2339 	sdram_org_config(cap_info, &sdram_params->base, &sys_reg2,  in dram_all_config()
2344 	cs_cap[0] = sdram_get_cs_cap(cap_info, 0, dram_type);  in dram_all_config()
2345 	cs_cap[1] = sdram_get_cs_cap(cap_info, 1, dram_type);  in dram_all_config()
2347 	if (cap_info->rank == 2) {  in dram_all_config()
2394 	struct sdram_cap_info *cap_info = &sdram_params->ch.cap_info;  in ddr_set_atags()  local
2405 	cs_cap[0] = sdram_get_cs_cap(cap_info, 0, dram_type);  in ddr_set_atags()
2406 	cs_cap[1] = sdram_get_cs_cap(cap_info, 1, dram_type);  in ddr_set_atags()
2422 	if (cap_info->row_3_4) {  in ddr_set_atags()
2466 	sdram_print_ddr_info(&sdram_params->ch.cap_info,  in print_ddr_info()
2494 	struct sdram_cap_info *cap_info;  in check_lp4_rzqi()  local
2500 	cap_info = &sdram_params->ch.cap_info;  in check_lp4_rzqi()
2501 	if (cap_info->dbw == 0) {  in check_lp4_rzqi()
2502 		cs = cap_info->rank - 1;  in check_lp4_rzqi()
2509 		for (cs = 0; cs < cap_info->rank; cs++) {  in check_lp4_rzqi()
2523 	struct sdram_cap_info *cap_info = &sdram_params->ch.cap_info;  in modify_ddr34_bw_byte_map()  local
2549 	cap_info->bw = byte / 2;  in modify_ddr34_bw_byte_map()
2560 		pctl_remodify_sdram_params(&sdram_params->pctl_regs, cap_info, dramtype);  in modify_ddr34_bw_byte_map()
2590 	if (sdram_params->ch.cap_info.bw == 2) {  in sdram_init_()
2614 	sdram_params->ch.cap_info.ddrconfig = calculate_ddrconfig(sdram_params);  in sdram_init_()
2689 	if (post_init != 0 && sdram_params->ch.cap_info.rank == 2) {  in sdram_init_()
2713 	struct sdram_cap_info *cap_info = &sdram_params->ch.cap_info;  in dram_detect_cap()  local
2739 			if (sdram_detect_col(cap_info, coltmp) != 0)  in dram_detect_cap()
2742 			sdram_detect_bank(cap_info, pctl_base, coltmp, bktmp);  in dram_detect_cap()
2744 				sdram_detect_dbw(cap_info, dram_type);  in dram_detect_cap()
2750 			cap_info->col = 10;  in dram_detect_cap()
2751 			cap_info->bk = 2;  in dram_detect_cap()
2752 			sdram_detect_bg(cap_info, pctl_base, coltmp);  in dram_detect_cap()
2755 		if (sdram_detect_row(cap_info, coltmp, bktmp, rowtmp) != 0)  in dram_detect_cap()
2758 		sdram_detect_row_3_4(cap_info, coltmp, bktmp);  in dram_detect_cap()
2760 		cap_info->col = 10;  in dram_detect_cap()
2761 		cap_info->bk = 3;  in dram_detect_cap()
2763 		cap_info->dbw = ((mr8 >> 6) & 0x3) == 0 ? 1 : 0;  in dram_detect_cap()
2766 			cap_info->cs0_row = 14 + (mr8 + 1) / 2;  in dram_detect_cap()
2768 			cap_info->cs0_row = 13;  in dram_detect_cap()
2773 		if (cap_info->dbw == 0)  in dram_detect_cap()
2774 			cap_info->cs0_row++;  in dram_detect_cap()
2775 		cap_info->row_3_4 = mr8 % 2 == 1 ? 1 : 0;  in dram_detect_cap()
2776 		if (cap_info->cs0_row >= 17) {  in dram_detect_cap()
2792 	cap_info->rank = cs + 1;  in dram_detect_cap()
2798 			cap_info->bw = 2;  in dram_detect_cap()
2810 				cap_info->bw = 1;  in dram_detect_cap()
2812 				cap_info->bw = 0;  in dram_detect_cap()
2818 	cap_info->cs0_high16bit_row = cap_info->cs0_row;  in dram_detect_cap()
2820 		cap_info->cs1_row = cap_info->cs0_row;  in dram_detect_cap()
2821 		cap_info->cs1_high16bit_row = cap_info->cs0_row;  in dram_detect_cap()
2823 		cap_info->cs1_row = 0;  in dram_detect_cap()
2824 		cap_info->cs1_high16bit_row = 0;  in dram_detect_cap()
2828 		sdram_detect_dbw(cap_info, dram_type);  in dram_detect_cap()
2839 	struct sdram_cap_info *cap_info = &sdram_params->ch.cap_info;  in dram_detect_cs1_row()  local
2850 	if (cap_info->rank == 2) {  in dram_detect_cs1_row()
2859 			if (cap_info->dbw == 0)  in dram_detect_cs1_row()
2860 				bktmp = cap_info->bk + 2;  in dram_detect_cs1_row()
2862 				bktmp = cap_info->bk + 1;  in dram_detect_cs1_row()
2864 			bktmp = cap_info->bk;  in dram_detect_cs1_row()
2866 		bw = cap_info->bw;  in dram_detect_cs1_row()
2867 		coltmp = cap_info->col;  in dram_detect_cs1_row()
2878 		row = (cap_info->cs0_row > max_row) ? max_row :  in dram_detect_cs1_row()
2879 			cap_info->cs0_row;  in dram_detect_cs1_row()
2907 	struct sdram_cap_info *cap_info = &sdram_params->ch.cap_info;  in sdram_init_detect()  local
2931 	pctl_remodify_sdram_params(&sdram_params->pctl_regs, cap_info,  in sdram_init_detect()
2937 	cap_info->cs1_row =  in sdram_init_detect()
2939 	if (cap_info->cs1_row) {  in sdram_init_detect()
2942 		SYS_REG_ENC_CS1_ROW(cap_info->cs1_row,  in sdram_init_detect()
2948 	sdram_detect_high_row(cap_info, sdram_params->base.dramtype);  in sdram_init_detect()
3261 			     struct sdram_cap_info *cap_info, u32 dram_type,  in pctl_modify_trfc()  argument
3271 	cs0_cap = sdram_get_cs_cap(cap_info, 0, dram_type);  in pctl_modify_trfc()
3272 	die_cap = (u32)(cs0_cap >> (20 + (cap_info->bw - cap_info->dbw)));  in pctl_modify_trfc()
3396 	sdram_params_new->ch.cap_info.rank = sdram_params->ch.cap_info.rank;  in ddr_set_rate()
3397 	sdram_params_new->ch.cap_info.bw = sdram_params->ch.cap_info.bw;  in ddr_set_rate()
3400 			 &sdram_params->ch.cap_info, dramtype, freq);  in ddr_set_rate()
3721 				  (u8)sdram_params->ch.cap_info.rank);  in sdram_init()