Lines Matching refs:PCTL2_MR_MASK
873 PCTL2_MR_MASK << PCTL2_LPDDR4_MR12_SHIFT, in set_lp4_vref()
878 PCTL2_MR_MASK << PCTL2_LPDDR4_MR14_SHIFT, in set_lp4_vref()
1095 mr1_mr3 = mr1_mr3 >> PCTL2_DDR34_MR1_SHIFT & PCTL2_MR_MASK; in set_ds_odt()
1099 mr1_mr3 = mr1_mr3 >> PCTL2_LPDDR234_MR3_SHIFT & PCTL2_MR_MASK; in set_ds_odt()
1167 mr11 = mr11 >> PCTL2_LPDDR4_MR11_SHIFT & PCTL2_MR_MASK; in set_ds_odt()
1179 PCTL2_MR_MASK << PCTL2_LPDDR4_MR11_SHIFT, in set_ds_odt()
1186 mr22 = mr22 >> PCTL2_LPDDR4_MR22_SHIFT & PCTL2_MR_MASK; in set_ds_odt()
1202 PCTL2_MR_MASK << PCTL2_LPDDR4_MR22_SHIFT, in set_ds_odt()
1211 PCTL2_MR_MASK << PCTL2_DDR34_MR1_SHIFT, in set_ds_odt()
1218 PCTL2_MR_MASK << PCTL2_LPDDR234_MR3_SHIFT, in set_ds_odt()
1604 mr4_d4 = readl(pctl_base + DDR_PCTL2_INIT6) >> PCTL2_DDR4_MR4_SHIFT & PCTL2_MR_MASK; in data_training_rg()
1932 pctl_write_mr(dram->pctl, 3, 2, mr_tmp & PCTL2_MR_MASK, in data_training_wr()
2637 mr_tmp >> PCTL2_LPDDR4_MR11_SHIFT & PCTL2_MR_MASK, in sdram_init_()
2641 mr_tmp >> PCTL2_LPDDR4_MR12_SHIFT & PCTL2_MR_MASK, in sdram_init_()
2647 mr_tmp >> PCTL2_LPDDR4_MR22_SHIFT & PCTL2_MR_MASK, in sdram_init_()
2650 mr_tmp = readl(pctl_base + DDR_PCTL2_INIT7) >> PCTL2_DDR4_MR6_SHIFT & PCTL2_MR_MASK; in sdram_init_()
2686 mr_tmp >> PCTL2_LPDDR4_MR14_SHIFT & PCTL2_MR_MASK, in sdram_init_()
3075 PCTL2_MR_MASK) & (~(BIT(7) | BIT(6)))) | in pre_set_rate()
3078 PCTL2_MR_MASK) & (~(BIT(7) | BIT(6)))) | in pre_set_rate()
3084 PCTL2_MR_MASK, in pre_set_rate()
3086 writel(mr_tmp >> PCTL2_LPDDR234_MR3_SHIFT & PCTL2_MR_MASK, in pre_set_rate()
3094 PCTL2_MR_MASK, in pre_set_rate()
3096 writel(mr_tmp >> PCTL2_LPDDR234_MR1_SHIFT & PCTL2_MR_MASK, in pre_set_rate()
3099 pctl_write_mr(dram->pctl, 3, 2, mr_tmp & PCTL2_MR_MASK, in pre_set_rate()
3101 writel(mr_tmp & PCTL2_MR_MASK, in pre_set_rate()
3108 mr_tmp >> PCTL2_LPDDR4_MR11_SHIFT & PCTL2_MR_MASK, in pre_set_rate()
3110 writel(mr_tmp >> PCTL2_LPDDR4_MR11_SHIFT & PCTL2_MR_MASK, in pre_set_rate()
3114 mr_tmp >> PCTL2_LPDDR4_MR12_SHIFT & PCTL2_MR_MASK, in pre_set_rate()
3121 mr_tmp >> PCTL2_LPDDR4_MR22_SHIFT & PCTL2_MR_MASK, in pre_set_rate()
3123 writel(mr_tmp >> PCTL2_LPDDR4_MR22_SHIFT & PCTL2_MR_MASK, in pre_set_rate()
3127 mr_tmp >> PCTL2_LPDDR4_MR14_SHIFT & PCTL2_MR_MASK, in pre_set_rate()
3129 writel(mr_tmp >> PCTL2_LPDDR4_MR14_SHIFT & PCTL2_MR_MASK, in pre_set_rate()
3175 temp = (temp >> PCTL2_DDR34_MR1_SHIFT) & PCTL2_MR_MASK; in save_fsp_param()
3182 temp = (temp >> PCTL2_DDR34_MR1_SHIFT) & PCTL2_MR_MASK; in save_fsp_param()
3189 temp = (temp >> PCTL2_LPDDR234_MR3_SHIFT) & PCTL2_MR_MASK; in save_fsp_param()
3198 temp = (temp >> PCTL2_LPDDR234_MR3_SHIFT) & PCTL2_MR_MASK; in save_fsp_param()
3203 temp = (temp >> PCTL2_LPDDR4_MR11_SHIFT) & PCTL2_MR_MASK; in save_fsp_param()
3418 cur_init3 &= PCTL2_MR_MASK; in ddr_set_rate()
3506 PCTL2_MR_MASK, in ddr_set_rate()
3508 pctl_write_mr(dram->pctl, 3, 2, dst_init3 & PCTL2_MR_MASK, in ddr_set_rate()
3512 PCTL2_MR_MASK, in ddr_set_rate()
3516 pctl_write_mr(dram->pctl, 3, 1, dst_init3 & PCTL2_MR_MASK, in ddr_set_rate()
3521 PCTL2_MR_MASK) | DDR3_DLL_RESET, in ddr_set_rate()
3527 PCTL2_MR_MASK) & (~DDR3_DLL_RESET), in ddr_set_rate()
3531 PCTL2_MR_MASK), dramtype); in ddr_set_rate()
3533 pctl_write_mr(dram->pctl, 3, 3, mr_tmp & PCTL2_MR_MASK, in ddr_set_rate()
3539 PCTL2_MR_MASK, in ddr_set_rate()
3543 PCTL2_MR_MASK, in ddr_set_rate()
3551 PCTL2_MR_MASK, dramtype); in ddr_set_rate()
3554 PCTL2_MR_MASK, dramtype); in ddr_set_rate()
3557 PCTL2_MR_MASK, in ddr_set_rate()
3563 PCTL2_MR_MASK) & (~(BIT(7)))) | in ddr_set_rate()