Lines Matching refs:i
402 u32 i, tmp; in calculate_ddrconfig() local
419 for (i = 17; i < 21; i++) { in calculate_ddrconfig()
421 (ddr4_cfg_2_rbc[i - 10] & 0xf)) && in calculate_ddrconfig()
423 (ddr4_cfg_2_rbc[i - 10] & 0x70))) { in calculate_ddrconfig()
424 ddrconf = i; in calculate_ddrconfig()
431 for (i = 10; i < 21; i++) { in calculate_ddrconfig()
432 if (((tmp & 0xf) == (ddr4_cfg_2_rbc[i - 10] & 0xf)) && in calculate_ddrconfig()
433 ((tmp & 0x70) <= (ddr4_cfg_2_rbc[i - 10] & 0x70)) && in calculate_ddrconfig()
434 ((tmp & 0x80) <= (ddr4_cfg_2_rbc[i - 10] & 0x80))) { in calculate_ddrconfig()
435 ddrconf = i; in calculate_ddrconfig()
441 for (i = 5; i < 8; i++) { in calculate_ddrconfig()
442 if (((bw + col - 10) == (ddr_cfg_2_rbc[i] & in calculate_ddrconfig()
444 ((row - 13) << 5) <= (ddr_cfg_2_rbc[i] & in calculate_ddrconfig()
446 ddrconf = i; in calculate_ddrconfig()
457 for (i = 0; i < 9; i++) in calculate_ddrconfig()
458 if (((tmp & 0x1f) == (ddr_cfg_2_rbc[i] & 0x1f)) && in calculate_ddrconfig()
460 (ddr_cfg_2_rbc[i] & (7 << 5))) && in calculate_ddrconfig()
462 (ddr_cfg_2_rbc[i] & (1 << 8)))) { in calculate_ddrconfig()
463 ddrconf = i; in calculate_ddrconfig()
467 for (i = 0; i < 7; i++) in calculate_ddrconfig()
468 if (((tmp & 0x1f) == (ddr_cfg_2_rbc_p2[i] & 0x1f)) && in calculate_ddrconfig()
470 (ddr_cfg_2_rbc_p2[i] & (7 << 5))) && in calculate_ddrconfig()
472 (ddr_cfg_2_rbc_p2[i] & (1 << 8)))) { in calculate_ddrconfig()
473 ddrconf = i + 22; in calculate_ddrconfig()
487 for (i = 0; i < ARRAY_SIZE(d4_rbc_2_d3_rbc) ; i++) { in calculate_ddrconfig()
488 if (ddrconf == d4_rbc_2_d3_rbc[i][0]) { in calculate_ddrconfig()
492 ddrconf = d4_rbc_2_d3_rbc[i][1]; in calculate_ddrconfig()
529 u32 i, row; in set_ctl_address_map() local
533 for (i = 0; i < ARRAY_SIZE(d4_rbc_2_d3_rbc) ; i++) { in set_ctl_address_map()
534 if (ddrconf == d4_rbc_2_d3_rbc[i][1]) { in set_ctl_address_map()
535 ddrconf = d4_rbc_2_d3_rbc[i][0]; in set_ctl_address_map()
550 for (i = 17; i >= row; i--) in set_ctl_address_map()
552 ((i - 12) * 8 / 32) * 4, in set_ctl_address_map()
553 0xf << ((i - 12) * 8 % 32)); in set_ctl_address_map()
891 u32 i, j, tmp; in set_ds_odt() local
977 for (i = ARRAY_SIZE(d3_phy_drv_2_ohm) - 1; ; i--) { in set_ds_odt()
978 if (phy_dq_drv_ohm <= *(*(p_drv + i) + 1)) { in set_ds_odt()
979 phy_dq_drv = **(p_drv + i); in set_ds_odt()
982 if (i == 0) in set_ds_odt()
985 for (i = ARRAY_SIZE(d3_phy_drv_2_ohm) - 1; ; i--) { in set_ds_odt()
986 if (phy_clk_drv_ohm <= *(*(p_drv + i) + 1)) { in set_ds_odt()
987 phy_clk_drv = **(p_drv + i); in set_ds_odt()
990 if (i == 0) in set_ds_odt()
993 for (i = ARRAY_SIZE(d3_phy_drv_2_ohm) - 1; ; i--) { in set_ds_odt()
994 if (phy_ca_drv_ohm <= *(*(p_drv + i) + 1)) { in set_ds_odt()
995 phy_ca_drv = **(p_drv + i); in set_ds_odt()
998 if (i == 0) in set_ds_odt()
1004 for (i = ARRAY_SIZE(d4lp3_phy_odt_2_ohm) - 1; ; i--) { in set_ds_odt()
1005 if (phy_odt_ohm <= *(*(p_odt + i) + 1)) { in set_ds_odt()
1006 phy_odt = **(p_odt + i); in set_ds_odt()
1009 if (i == 0) in set_ds_odt()
1063 for (i = 0; i < 4; i++) { in set_ds_odt()
1064 j = 0x110 + i * 0x10; in set_ds_odt()
1069 writel(vref_inner, PHY_REG(phy_base, 0x118 + i * 0x10)); in set_ds_odt()
1071 clrsetbits_le32(PHY_REG(phy_base, 0x114 + i * 0x10), in set_ds_odt()
1074 clrbits_le32(PHY_REG(phy_base, 0x114 + i * 0x10), BIT(5)); in set_ds_odt()
1076 clrsetbits_le32(PHY_REG(phy_base, 0x117 + i * 0x10), in set_ds_odt()
1252 u32 i, dq_map, tmp; in phy_cfg() local
1258 for (i = 0; sdram_params->phy_regs.phy[i][0] != 0xFFFFFFFF; i++) { in phy_cfg()
1259 writel(sdram_params->phy_regs.phy[i][1], in phy_cfg()
1260 phy_base + sdram_params->phy_regs.phy[i][0]); in phy_cfg()
1265 for (i = 0; i < 4; i++) { in phy_cfg()
1266 if (((dq_map >> (i * 2)) & 0x3) == 0) { in phy_cfg()
1267 byte0 = i; in phy_cfg()
1271 for (i = 0; i < 4; i++) { in phy_cfg()
1272 if (((dq_map >> (i * 2)) & 0x3) == 1) { in phy_cfg()
1273 byte1 = i; in phy_cfg()
1318 u32 i, temp; in read_mr() local
1333 for (i = 0; i < 8; i++) in read_mr()
1334 ret |= ((temp >> i) & 0x1) << in read_mr()
1335 ((map_info->lp3_dq0_7_map >> (i * 4)) & 0xf); in read_mr()
1371 u32 group, i, tmp; in record_dq_prebit() local
1375 for (i = 0; i < ARRAY_SIZE(dq_sel); i++) { in record_dq_prebit()
1377 writel(dq_sel[i][0], PHY_REG(phy_base, in record_dq_prebit()
1381 grp_addr[group] + dq_sel[i][1])); in record_dq_prebit()
1384 writel(dq_sel[i][0], PHY_REG(phy_base, in record_dq_prebit()
1388 grp_addr[group] + dq_sel[i][2])); in record_dq_prebit()
1434 u32 i, cs_en, tmp; in modify_ca_deskew() local
1451 for (i = 0; i < 0x20; i++) { in modify_ca_deskew()
1455 tmp = readl(PHY_REG(phy_base, 0x150 + i)) + in modify_ca_deskew()
1457 writel(tmp, PHY_REG(phy_base, 0x150 + i)); in modify_ca_deskew()
1483 u32 i, j, offset = 0; in get_min_value() local
1492 for (i = 0; i < 0x20; i++) in get_min_value()
1493 min = MIN(min, readl(PHY_REG(phy_base, 0x150 + i))); in get_min_value()
1499 for (i = 0; i < 11; i++) in get_min_value()
1503 i))); in get_min_value()
1536 u32 i, j, tmp, offset; in modify_dq_deskew() local
1549 for (i = 0; i < 0x9; i++) { in modify_dq_deskew()
1555 i)); in modify_dq_deskew()
1556 writel(tmp, PHY_REG(phy_base, dqs_dq_skew_adr[j] + i)); in modify_dq_deskew()
1578 u32 i, j; in data_training_rg() local
1588 for (i = 0; i < 4; i++) { in data_training_rg()
1589 j = 0x110 + i * 0x10; in data_training_rg()
1630 for (i = 0; i < 4; i++) { in data_training_rg()
1631 j = 0x110 + i * 0x10; in data_training_rg()
1720 u32 i; in data_training_rd() local
1727 for (i = 0; i < 4; i++) in data_training_rd()
1729 PHY_REG(phy_base, 0x118 + i * 0x10)); in data_training_rd()
1765 for (i = 0; i < 4; i++) { in data_training_rd()
1767 ((i % 4) * 8)) & 0xff, in data_training_rd()
1768 PHY_REG(phy_base, 0x238 + i)); in data_training_rd()
1770 ((i % 4) * 8)) & 0xff, in data_training_rd()
1771 PHY_REG(phy_base, 0x2b8 + i)); in data_training_rd()
1814 for (i = 0; i < 4; i++) in data_training_rd()
1816 PHY_REG(phy_base, 0x118 + i * 0x10)); in data_training_rd()
1987 int i, j, clk_skew; in get_wrlvl_val() local
2003 for (i = 0; i < 4; i++) in get_wrlvl_val()
2004 wrlvl_result[j][i] = in get_wrlvl_val()
2005 (readl(PHY_REG(phy_base, wrlvl_result_offset[j][i])) & 0x3f) - in get_wrlvl_val()
2017 int i; in init_rw_trn_result_struct() local
2022 for (i = 0; i < FSP_NUM; i++) in init_rw_trn_result_struct()
2023 result->fsp_mhz[i] = 0; in init_rw_trn_result_struct()
2102 u32 i, j; in high_freq_training() local
2113 for (i = 0; i < ARRAY_SIZE(wrlvl_result[0]); i++) { in high_freq_training()
2114 if ((byte_en & BIT(i)) != 0) in high_freq_training()
2115 dqs_skew += wrlvl_result[j][i]; in high_freq_training()
2127 for (i = 0; i < ARRAY_SIZE(wrlvl_result[0]); i++) { in high_freq_training()
2128 if ((byte_en & BIT(i)) != 0) in high_freq_training()
2129 min_val = MIN(wrlvl_result[j][i], min_val); in high_freq_training()
2528 int i; in modify_ddr34_bw_byte_map() local
2537 for (i = 0; i < 4; i++) { in modify_ddr34_bw_byte_map()
2538 if ((rg_result & BIT(i)) == 0) { in modify_ddr34_bw_byte_map()
2539 byte_map |= byte << (i * 2); in modify_ddr34_bw_byte_map()
2550 for (i = 0; i < 4; i++) { in modify_ddr34_bw_byte_map()
2551 if ((rg_result & BIT(i)) != 0) { in modify_ddr34_bw_byte_map()
2552 byte_map |= byte << (i * 2); in modify_ddr34_bw_byte_map()
2724 u32 i, dq_map; in dram_detect_cap() local
2801 for (i = 0; i < 4; i++) { in dram_detect_cap()
2802 if (((dq_map >> (i * 2)) & 0x3) == 0) in dram_detect_cap()
2803 byte0 = i; in dram_detect_cap()
2804 if (((dq_map >> (i * 2)) & 0x3) == 1) in dram_detect_cap()
2805 byte1 = i; in dram_detect_cap()
2956 u32 i; in get_default_sdram_config() local
2970 for (i = 0; i < ARRAY_SIZE(sdram_configs); i++) { in get_default_sdram_config()
2971 if (sdram_configs[i].base.ddr_freq == 0 || in get_default_sdram_config()
2972 freq_mhz < sdram_configs[i].base.ddr_freq) in get_default_sdram_config()
2975 offset = i == 0 ? 0 : i - 1; in get_default_sdram_config()
3014 u32 i, j, find; in pre_set_rate() local
3023 for (i = 0, find = 0; i < ARRAY_SIZE(pctl_need_update_reg); i++) { in pre_set_rate()
3027 pctl_need_update_reg[i]) { in pre_set_rate()
3030 pctl_need_update_reg[i]); in pre_set_rate()
3054 for (i = 0, find = 0; i < ARRAY_SIZE(phy_need_update_reg); i++) { in pre_set_rate()
3058 phy_need_update_reg[i]) { in pre_set_rate()
3061 phy_need_update_reg[i]); in pre_set_rate()
3333 for (int i = 0; pctl_regs->pctl[i][0] != 0xffffffff; i++) { in pctl_modify_trfc() local
3334 switch (pctl_regs->pctl[i][0]) { in pctl_modify_trfc()
3336 tmp = pctl_regs->pctl[i][1]; in pctl_modify_trfc()
3340 pctl_regs->pctl[i][1] = tmp; in pctl_modify_trfc()
3345 tmp = pctl_regs->pctl[i][1]; in pctl_modify_trfc()
3359 pctl_regs->pctl[i][1] = tmp; in pctl_modify_trfc()
3366 tmp = pctl_regs->pctl[i][1]; in pctl_modify_trfc()
3370 pctl_regs->pctl[i][1] = tmp; in pctl_modify_trfc()