Lines Matching refs:ddr_timing_t
140 if (params_priv->ddr_timing_t.freq == 393) { in rkdclk_init()
159 if (params_priv->ddr_timing_t.freq == 800) { in rkdclk_init()
162 } else if (params_priv->ddr_timing_t.freq == 589) { in rkdclk_init()
165 } else if (params_priv->ddr_timing_t.freq == 451) { in rkdclk_init()
168 } else if (params_priv->ddr_timing_t.freq == 393) { in rkdclk_init()
171 } else if (params_priv->ddr_timing_t.freq == 294) { in rkdclk_init()
174 } else if (params_priv->ddr_timing_t.freq == 225) { in rkdclk_init()
184 if (params_priv->ddr_timing_t.freq == 800) { in rkdclk_init()
466 writel(BWRATIO_HALF_BW | params_priv->ddr_timing_t.noc_timing.d32, in ddr_msch_cfg()
468 writel(params_priv->ddr_timing_t.readlatency, in ddr_msch_cfg()
533 if (params_priv->ddr_timing_t.freq > in set_ds_odt()
591 if (params_priv->ddr_timing_t.freq == 451) in enable_ddr_standby()
593 else if (params_priv->ddr_timing_t.freq == 393) in enable_ddr_standby()
690 u32 nMHz = params_priv->ddr_timing_t.freq; in modify_sdram_params()
831 if (params_priv->ddr_timing_t.freq == 451) { in enable_low_power()
834 } else if (params_priv->ddr_timing_t.freq == 393) { in enable_low_power()