243 		     struct rk3288_sdram_params *sdram_params,  in pctl_cfg()  argument
248 	burstlen = (sdram_params->base.noc_timing >> 18) & 0x7;  in pctl_cfg()
249 	copy_to_reg(&pctl->togcnt1u, &sdram_params->pctl_timing.togcnt1u,  in pctl_cfg()
250 		    sizeof(sdram_params->pctl_timing));  in pctl_cfg()
251 	switch (sdram_params->base.dramtype) {  in pctl_cfg()
253 		writel(sdram_params->pctl_timing.tcl - 1,  in pctl_cfg()
255 		writel(sdram_params->pctl_timing.tcwl,  in pctl_cfg()
266 				   sdram_params->base.odt);  in pctl_cfg()
269 		if (sdram_params->phy_timing.mr[1] & DDR3_DLL_DISABLE) {  in pctl_cfg()
270 			writel(sdram_params->pctl_timing.tcl - 3,  in pctl_cfg()
273 			writel(sdram_params->pctl_timing.tcl - 2,  in pctl_cfg()
276 		writel(sdram_params->pctl_timing.tcwl - 1,  in pctl_cfg()
293 		    struct rk3288_sdram_params *sdram_params)  in phy_cfg()  argument
297 	uint ddr_freq_mhz = sdram_params->base.ddr_freq / 1000000;  in phy_cfg()
303 	copy_to_reg(&publ->dtpr[0], &sdram_params->phy_timing.dtpr0,  in phy_cfg()
304 		    sizeof(sdram_params->phy_timing));  in phy_cfg()
305 	writel(sdram_params->base.noc_timing, &msch->ddrtiming);  in phy_cfg()
307 	writel(sdram_params->base.noc_activate, &msch->activate);  in phy_cfg()
320 	switch (sdram_params->base.dramtype) {  in phy_cfg()
348 	if (sdram_params->base.odt) {  in phy_cfg()
476 			 struct rk3288_sdram_params *sdram_params)  in data_training()  argument
489 	if (sdram_params->base.dramtype != LPDDR3)  in data_training()
491 	rank = sdram_params->ch[channel].rank | 1;  in data_training()
529 	if (sdram_params->base.dramtype != LPDDR3)  in data_training()
533 	writel(sdram_params->pctl_timing.trefi, &pctl->trefi);  in data_training()
579 			 struct rk3288_sdram_params *sdram_params)  in dram_cfg_rbc()  argument
583 	if (sdram_params->ch[chnum].bk == 3)  in dram_cfg_rbc()
589 	writel(sdram_params->base.ddrconfig, &chan->msch->ddrconf);  in dram_cfg_rbc()
593 			    struct rk3288_sdram_params *sdram_params)  in dram_all_config()  argument
598 	sys_reg |= sdram_params->base.dramtype << SYS_REG_DDRTYPE_SHIFT;  in dram_all_config()
599 	sys_reg |= (sdram_params->num_channels - 1) << SYS_REG_NUM_CH_SHIFT;  in dram_all_config()
600 	for (chan = 0; chan < sdram_params->num_channels; chan++) {  in dram_all_config()
602 			&sdram_params->ch[chan];  in dram_all_config()
614 		dram_cfg_rbc(&dram->chan[chan], chan, sdram_params);  in dram_all_config()
617 	rk_clrsetreg(&dram->sgrf->soc_con2, 0x1f, sdram_params->base.stride);  in dram_all_config()
621 		struct rk3288_sdram_params *sdram_params)  in sdram_rank_bw_detect()  argument
628 	if (data_training(chan, channel, sdram_params) < 0) {  in sdram_rank_bw_detect()
636 			sdram_params->num_channels = 1;  in sdram_rank_bw_detect()
641 			sdram_params->ch[channel].rank = 1;  in sdram_rank_bw_detect()
643 					sdram_params->ch[channel].rank << 18);  in sdram_rank_bw_detect()
648 			sdram_params->ch[channel].bw = 1;  in sdram_rank_bw_detect()
650 					    sdram_params->ch[channel].bw,  in sdram_rank_bw_detect()
656 	sdram_params->ch[channel].dbw = sdram_params->ch[channel].bw;  in sdram_rank_bw_detect()
659 	    (data_training(chan, channel, sdram_params) < 0)) {  in sdram_rank_bw_detect()
660 		if (sdram_params->base.dramtype == LPDDR3) {  in sdram_rank_bw_detect()
674 		struct rk3288_sdram_params *sdram_params)  in sdram_col_row_detect()  argument
687 			(1 << (col + sdram_params->ch[channel].bw - 1));  in sdram_col_row_detect()
698 		sdram_params->ch[channel].col = col;  in sdram_col_row_detect()
717 		sdram_params->ch[channel].cs1_row = row;  in sdram_col_row_detect()
718 		sdram_params->ch[channel].row_3_4 = 0;  in sdram_col_row_detect()
720 		sdram_params->ch[channel].cs0_row = row;  in sdram_col_row_detect()
727 static int sdram_get_biu_config(struct rk3288_sdram_params *sdram_params)  in sdram_get_biu_config()  argument
731 	tmp = sdram_params->ch[0].col - 9;  in sdram_get_biu_config()
732 	tmp -= (sdram_params->ch[0].bw == 2) ? 0 : 1;  in sdram_get_biu_config()
733 	tmp |= ((sdram_params->ch[0].cs0_row - 12) << 4);  in sdram_get_biu_config()
742 		sdram_params->base.ddrconfig = i;  in sdram_get_biu_config()
748 static int sdram_get_stride(struct rk3288_sdram_params *sdram_params)  in sdram_get_stride()  argument
752 	long cap = sdram_params->num_channels * (1u <<  in sdram_get_stride()
753 			(sdram_params->ch[0].cs0_row +  in sdram_get_stride()
754 			 sdram_params->ch[0].col +  in sdram_get_stride()
755 			 (sdram_params->ch[0].rank - 1) +  in sdram_get_stride()
756 			 sdram_params->ch[0].bw +  in sdram_get_stride()
778 	sdram_params->base.stride = stride;  in sdram_get_stride()
784 		      struct rk3288_sdram_params *sdram_params)  in sdram_init()  argument
791 	if ((sdram_params->base.dramtype == DDR3 &&  in sdram_init()
792 	     sdram_params->base.ddr_freq > 800000000) ||  in sdram_init()
793 	    (sdram_params->base.dramtype == LPDDR3 &&  in sdram_init()
794 	     sdram_params->base.ddr_freq > 533000000)) {  in sdram_init()
800 	ret = clk_set_rate(&dram->ddr_clk, sdram_params->base.ddr_freq);  in sdram_init()
818 		phy_dll_bypass_set(publ, sdram_params->base.ddr_freq);  in sdram_init()
820 		dfi_cfg(pctl, sdram_params->base.dramtype);  in sdram_init()
822 		pctl_cfg(channel, pctl, sdram_params, dram->grf);  in sdram_init()
824 		phy_cfg(chan, channel, sdram_params);  in sdram_init()
832 		memory_init(publ, sdram_params->base.dramtype);  in sdram_init()
835 		if (sdram_params->base.dramtype == LPDDR3) {  in sdram_init()
843 					sdram_params->phy_timing.mr[1]);  in sdram_init()
846 					sdram_params->phy_timing.mr[2]);  in sdram_init()
849 					sdram_params->phy_timing.mr[3]);  in sdram_init()
854 		sdram_params->ch[channel].bw = 2;  in sdram_init()
856 				    sdram_params->ch[channel].bw, dram->grf);  in sdram_init()
863 		sdram_params->ch[channel].rank = 2,  in sdram_init()
865 				(sdram_params->ch[channel].rank | 1) << 18);  in sdram_init()
874 		if (sdram_params->base.dramtype == LPDDR3) {  in sdram_init()
878 					sdram_params->ch[channel].rank | 1,  in sdram_init()
880 					sdram_params->base.odt ? 3 : 0);  in sdram_init()
893 		sdram_rank_bw_detect(dram, channel, sdram_params);  in sdram_init()
895 		if (sdram_params->base.dramtype == LPDDR3) {  in sdram_init()
904 		sdram_params->ch[channel].bk = 3;  in sdram_init()
906 		ret = sdram_col_row_detect(dram, channel, sdram_params);  in sdram_init()
911 	ret = sdram_get_biu_config(sdram_params);  in sdram_init()
915 	ret = sdram_get_stride(sdram_params);  in sdram_init()
919 	dram_all_config(dram, sdram_params);  in sdram_init()