230 		     struct rk3188_sdram_params *sdram_params,  in pctl_cfg()  argument
233 	copy_to_reg(&pctl->togcnt1u, &sdram_params->pctl_timing.togcnt1u,  in pctl_cfg()
234 		    sizeof(sdram_params->pctl_timing));  in pctl_cfg()
235 	switch (sdram_params->base.dramtype) {  in pctl_cfg()
237 		if (sdram_params->phy_timing.mr[1] & DDR3_DLL_DISABLE) {  in pctl_cfg()
238 			writel(sdram_params->pctl_timing.tcl - 3,  in pctl_cfg()
241 			writel(sdram_params->pctl_timing.tcl - 2,  in pctl_cfg()
244 		writel(sdram_params->pctl_timing.tcwl - 1,  in pctl_cfg()
259 		    struct rk3188_sdram_params *sdram_params)  in phy_cfg()  argument
263 	uint ddr_freq_mhz = sdram_params->base.ddr_freq / 1000000;  in phy_cfg()
269 	copy_to_reg(&publ->dtpr[0], &sdram_params->phy_timing.dtpr0,  in phy_cfg()
270 		    sizeof(sdram_params->phy_timing));  in phy_cfg()
271 	writel(sdram_params->base.noc_timing, &msch->ddrtiming);  in phy_cfg()
283 	switch (sdram_params->base.dramtype) {  in phy_cfg()
290 	if (sdram_params->base.odt) {  in phy_cfg()
418 			 struct rk3188_sdram_params *sdram_params)  in data_training()  argument
431 	if (sdram_params->base.dramtype != LPDDR3)  in data_training()
433 	rank = sdram_params->ch[channel].rank | 1;  in data_training()
471 	if (sdram_params->base.dramtype != LPDDR3)  in data_training()
475 	writel(sdram_params->pctl_timing.trefi, &pctl->trefi);  in data_training()
522 			 struct rk3188_sdram_params *sdram_params)  in dram_cfg_rbc()  argument
526 	if (sdram_params->ch[chnum].bk == 3)  in dram_cfg_rbc()
532 	writel(sdram_params->base.ddrconfig, &chan->msch->ddrconf);  in dram_cfg_rbc()
536 			    struct rk3188_sdram_params *sdram_params)  in dram_all_config()  argument
541 	sys_reg |= sdram_params->base.dramtype << SYS_REG_DDRTYPE_SHIFT;  in dram_all_config()
542 	sys_reg |= (sdram_params->num_channels - 1) << SYS_REG_NUM_CH_SHIFT;  in dram_all_config()
543 	for (chan = 0; chan < sdram_params->num_channels; chan++) {  in dram_all_config()
545 			&sdram_params->ch[chan];  in dram_all_config()
557 		dram_cfg_rbc(&dram->chan[chan], chan, sdram_params);  in dram_all_config()
559 	if (sdram_params->ch[0].rank == 2)  in dram_all_config()
568 		struct rk3188_sdram_params *sdram_params)  in sdram_rank_bw_detect()  argument
577 	if (data_training(chan, channel, sdram_params) < 0) {  in sdram_rank_bw_detect()
588 			sdram_params->ch[channel].rank = 1;  in sdram_rank_bw_detect()
590 					sdram_params->ch[channel].rank << 18);  in sdram_rank_bw_detect()
595 			sdram_params->ch[channel].bw = 1;  in sdram_rank_bw_detect()
597 					    sdram_params->ch[channel].bw,  in sdram_rank_bw_detect()
603 	sdram_params->ch[channel].dbw = sdram_params->ch[channel].bw;  in sdram_rank_bw_detect()
606 	    (data_training(chan, channel, sdram_params) < 0)) {  in sdram_rank_bw_detect()
607 		if (sdram_params->base.dramtype == LPDDR3) {  in sdram_rank_bw_detect()
629 		struct rk3188_sdram_params *sdram_params)  in sdram_col_row_detect()  argument
642 			(1 << (col + sdram_params->ch[channel].bw - 1));  in sdram_col_row_detect()
653 		sdram_params->ch[channel].col = col;  in sdram_col_row_detect()
673 		sdram_params->ch[channel].cs1_row = row;  in sdram_col_row_detect()
674 		sdram_params->ch[channel].row_3_4 = 0;  in sdram_col_row_detect()
676 		sdram_params->ch[channel].cs0_row = row;  in sdram_col_row_detect()
683 static int sdram_get_biu_config(struct rk3188_sdram_params *sdram_params)  in sdram_get_biu_config()  argument
687 	row = sdram_params->ch[0].cs0_row;  in sdram_get_biu_config()
694 	tmp = sdram_params->ch[0].col - 9;  in sdram_get_biu_config()
695 	tmp -= (sdram_params->ch[0].bw == 2) ? 0 : 1;  in sdram_get_biu_config()
706 		sdram_params->base.ddrconfig = i;  in sdram_get_biu_config()
713 		      struct rk3188_sdram_params *sdram_params)  in sdram_init()  argument
719 	if ((sdram_params->base.dramtype == DDR3 &&  in sdram_init()
720 	     sdram_params->base.ddr_freq > 800000000)) {  in sdram_init()
725 	ret = clk_set_rate(&dram->ddr_clk, sdram_params->base.ddr_freq);  in sdram_init()
737 		phy_dll_bypass_set(publ, sdram_params->base.ddr_freq);  in sdram_init()
739 		dfi_cfg(pctl, sdram_params->base.dramtype);  in sdram_init()
741 		pctl_cfg(channel, pctl, sdram_params, dram->grf);  in sdram_init()
743 		phy_cfg(chan, channel, sdram_params);  in sdram_init()
751 		memory_init(publ, sdram_params->base.dramtype);  in sdram_init()
755 		sdram_params->ch[channel].bw = 2;  in sdram_init()
757 				    sdram_params->ch[channel].bw, dram->grf);  in sdram_init()
764 		sdram_params->ch[channel].rank = 2,  in sdram_init()
766 				(sdram_params->ch[channel].rank | 1) << 18);  in sdram_init()
777 		sdram_rank_bw_detect(dram, channel, sdram_params);  in sdram_init()
779 		if (sdram_params->base.dramtype == LPDDR3) {  in sdram_init()
788 		sdram_params->ch[channel].bk = 3;  in sdram_init()
790 		ret = sdram_col_row_detect(dram, channel, sdram_params);  in sdram_init()
795 	ret = sdram_get_biu_config(sdram_params);  in sdram_init()
799 	dram_all_config(dram, sdram_params);  in sdram_init()