111 		writel(mask, &pio->mux.pio3.ppddr);  in at91_mux_set_pullup()
130 	writel(mask, &pio->mux.pio2.asr);  in at91_mux_set_A_periph()
135 	writel(mask, &pio->mux.pio2.bsr);  in at91_mux_set_B_periph()
140 	writel(readl(&pio->mux.pio3.abcdsr1) & ~mask, &pio->mux.pio3.abcdsr1);  in at91_mux_pio3_set_A_periph()
141 	writel(readl(&pio->mux.pio3.abcdsr2) & ~mask, &pio->mux.pio3.abcdsr2);  in at91_mux_pio3_set_A_periph()
146 	writel(readl(&pio->mux.pio3.abcdsr1) | mask, &pio->mux.pio3.abcdsr1);  in at91_mux_pio3_set_B_periph()
147 	writel(readl(&pio->mux.pio3.abcdsr2) & ~mask, &pio->mux.pio3.abcdsr2);  in at91_mux_pio3_set_B_periph()
152 	writel(readl(&pio->mux.pio3.abcdsr1) & ~mask, &pio->mux.pio3.abcdsr1);  in at91_mux_pio3_set_C_periph()
153 	writel(readl(&pio->mux.pio3.abcdsr2) | mask, &pio->mux.pio3.abcdsr2);  in at91_mux_pio3_set_C_periph()
158 	writel(readl(&pio->mux.pio3.abcdsr1) | mask, &pio->mux.pio3.abcdsr1);  in at91_mux_pio3_set_D_periph()
159 	writel(readl(&pio->mux.pio3.abcdsr2) | mask, &pio->mux.pio3.abcdsr2);  in at91_mux_pio3_set_D_periph()
171 		writel(mask, &pio->mux.pio3.ifscdr);  in at91_mux_pio3_set_deglitch()
179 		writel(mask, &pio->mux.pio3.ifscer);  in at91_mux_pio3_set_debounce()
180 		writel(div & PIO_SCDR_DIV, &pio->mux.pio3.scdr);  in at91_mux_pio3_set_debounce()
183 		writel(mask, &pio->mux.pio3.ifscdr);  in at91_mux_pio3_set_debounce()
193 	writel(mask, (is_on ? &pio->mux.pio3.ppder : &pio->mux.pio3.ppddr));  in at91_mux_pio3_set_pulldown()
288 			struct at91_port *pio, u32 mask, enum at91_mux mux)  in at91_pmx_set()  argument
291 	switch (mux) {  in at91_pmx_set()
312 	if (mux)  in at91_pmx_set()
374 	enum at91_mux mux;  in at91_pinctrl_set_state()  local
394 		mux = *list++;  in at91_pinctrl_set_state()
404 		ret = at91_pmx_set(ops, pio, mask, mux);  in at91_pinctrl_set_state()