416 static int udphy_clk_init(struct rockchip_udphy *udphy, struct udevice *dev)  in udphy_clk_init()  argument
421 static int udphy_reset_init(struct rockchip_udphy *udphy, struct udevice *dev)  in udphy_reset_init()  argument
423 	const struct rockchip_udphy_cfg *cfg = udphy->cfgs;  in udphy_reset_init()
427 	udphy->rsts = devm_kcalloc(dev, cfg->num_rsts,  in udphy_reset_init()
428 				   sizeof(*udphy->rsts), GFP_KERNEL);  in udphy_reset_init()
429 	if (!udphy->rsts)  in udphy_reset_init()
435 		ret = reset_get_by_name(dev, name, &udphy->rsts[idx]);  in udphy_reset_init()
441 		reset_assert(&udphy->rsts[idx]);  in udphy_reset_init()
447 	devm_kfree(dev, udphy->rsts);  in udphy_reset_init()
463 static int udphy_reset_assert(struct rockchip_udphy *udphy, char *name)  in udphy_reset_assert()  argument
465 	const struct rockchip_udphy_cfg *cfg = udphy->cfgs;  in udphy_reset_assert()
472 	return reset_assert(&udphy->rsts[idx]);  in udphy_reset_assert()
475 static int udphy_reset_deassert(struct rockchip_udphy *udphy, char *name)  in udphy_reset_deassert()  argument
477 	const struct rockchip_udphy_cfg *cfg = udphy->cfgs;  in udphy_reset_deassert()
484 	return reset_deassert(&udphy->rsts[idx]);  in udphy_reset_deassert()
487 static void udphy_u3_port_disable(struct rockchip_udphy *udphy, u8 disable)  in udphy_u3_port_disable()  argument
489 	const struct rockchip_udphy_cfg *cfg = udphy->cfgs;  in udphy_u3_port_disable()
492 	preg = udphy->id ? &cfg->grfcfg.usb3otg1_cfg : &cfg->grfcfg.usb3otg0_cfg;  in udphy_u3_port_disable()
493 	grfreg_write(udphy->usbgrf, preg, disable);  in udphy_u3_port_disable()
497 static void udphy_usb_bvalid_enable(struct rockchip_udphy *udphy, u8 enable)  in udphy_usb_bvalid_enable()  argument
499 	const struct rockchip_udphy_cfg *cfg = udphy->cfgs;  in udphy_usb_bvalid_enable()
501 	grfreg_write(udphy->u2phygrf, &cfg->grfcfg.bvalid_phy_con, enable);  in udphy_usb_bvalid_enable()
502 	grfreg_write(udphy->u2phygrf, &cfg->grfcfg.bvalid_grf_con, enable);  in udphy_usb_bvalid_enable()
540 static int udphy_dplane_select(struct rockchip_udphy *udphy)  in udphy_dplane_select()  argument
542 	const struct rockchip_udphy_cfg *cfg = udphy->cfgs;  in udphy_dplane_select()
545 	switch (udphy->mode) {  in udphy_dplane_select()
547 		value |= 2 << udphy->dp_lane_sel[2] * 2;  in udphy_dplane_select()
548 		value |= 3 << udphy->dp_lane_sel[3] * 2;  in udphy_dplane_select()
550 		value |= 0 << udphy->dp_lane_sel[0] * 2;  in udphy_dplane_select()
551 		value |= 1 << udphy->dp_lane_sel[1] * 2;  in udphy_dplane_select()
559 	regmap_write(udphy->vogrf, cfg->vogrfcfg[udphy->id].dp_lane_reg,  in udphy_dplane_select()
561 		     FIELD_PREP(DP_AUX_DIN_SEL, udphy->dp_aux_din_sel) |  in udphy_dplane_select()
562 		     FIELD_PREP(DP_AUX_DOUT_SEL, udphy->dp_aux_dout_sel) | value);  in udphy_dplane_select()
567 static int udphy_dplane_get(struct rockchip_udphy *udphy)  in udphy_dplane_get()  argument
571 	switch (udphy->mode) {  in udphy_dplane_get()
588 static int udphy_dplane_enable(struct rockchip_udphy *udphy, int dp_lanes)  in udphy_dplane_enable()  argument
594 		val |= BIT(udphy->dp_lane_sel[i]);  in udphy_dplane_enable()
596 	regmap_update_bits(udphy->pma_regmap, CMN_LANE_MUX_AND_EN_OFFSET, CMN_DP_LANE_EN_ALL,  in udphy_dplane_enable()
600 		regmap_update_bits(udphy->pma_regmap, CMN_DP_RSTN_OFFSET,  in udphy_dplane_enable()
608 static int udphy_set_typec_default_mapping(struct rockchip_udphy *udphy)  in udphy_set_typec_default_mapping()  argument
610 	if (udphy->flip) {  in udphy_set_typec_default_mapping()
611 		udphy->dp_lane_sel[0] = 0;  in udphy_set_typec_default_mapping()
612 		udphy->dp_lane_sel[1] = 1;  in udphy_set_typec_default_mapping()
613 		udphy->dp_lane_sel[2] = 3;  in udphy_set_typec_default_mapping()
614 		udphy->dp_lane_sel[3] = 2;  in udphy_set_typec_default_mapping()
615 		udphy->lane_mux_sel[0] = PHY_LANE_MUX_DP;  in udphy_set_typec_default_mapping()
616 		udphy->lane_mux_sel[1] = PHY_LANE_MUX_DP;  in udphy_set_typec_default_mapping()
617 		udphy->lane_mux_sel[2] = PHY_LANE_MUX_USB;  in udphy_set_typec_default_mapping()
618 		udphy->lane_mux_sel[3] = PHY_LANE_MUX_USB;  in udphy_set_typec_default_mapping()
619 		udphy->dp_aux_dout_sel = PHY_AUX_DP_DATA_POL_INVERT;  in udphy_set_typec_default_mapping()
620 		udphy->dp_aux_din_sel = PHY_AUX_DP_DATA_POL_INVERT;  in udphy_set_typec_default_mapping()
622 		udphy->dp_lane_sel[0] = 2;  in udphy_set_typec_default_mapping()
623 		udphy->dp_lane_sel[1] = 3;  in udphy_set_typec_default_mapping()
624 		udphy->dp_lane_sel[2] = 1;  in udphy_set_typec_default_mapping()
625 		udphy->dp_lane_sel[3] = 0;  in udphy_set_typec_default_mapping()
626 		udphy->lane_mux_sel[0] = PHY_LANE_MUX_USB;  in udphy_set_typec_default_mapping()
627 		udphy->lane_mux_sel[1] = PHY_LANE_MUX_USB;  in udphy_set_typec_default_mapping()
628 		udphy->lane_mux_sel[2] = PHY_LANE_MUX_DP;  in udphy_set_typec_default_mapping()
629 		udphy->lane_mux_sel[3] = PHY_LANE_MUX_DP;  in udphy_set_typec_default_mapping()
630 		udphy->dp_aux_dout_sel = PHY_AUX_DP_DATA_POL_NORMAL;  in udphy_set_typec_default_mapping()
631 		udphy->dp_aux_din_sel = PHY_AUX_DP_DATA_POL_NORMAL;  in udphy_set_typec_default_mapping()
634 	udphy->mode = UDPHY_MODE_DP_USB;  in udphy_set_typec_default_mapping()
639 static int udphy_refclk_set(struct rockchip_udphy *udphy)  in udphy_refclk_set()  argument
644 	ret = __regmap_multi_reg_write(udphy->pma_regmap, udphy_24m_refclk_cfg,  in udphy_refclk_set()
652 static int udphy_status_check(struct rockchip_udphy *udphy)  in udphy_status_check()  argument
658 	if (udphy->mode & UDPHY_MODE_USB) {  in udphy_status_check()
659 		ret = regmap_read_poll_timeout(udphy->pma_regmap, CMN_ANA_LCPLL_DONE_OFFSET,  in udphy_status_check()
663 			dev_err(udphy->dev, "cmn ana lcpll lock timeout\n");  in udphy_status_check()
668 	if (udphy->mode & UDPHY_MODE_USB) {  in udphy_status_check()
669 		if (!udphy->flip) {  in udphy_status_check()
670 			ret = regmap_read_poll_timeout(udphy->pma_regmap,  in udphy_status_check()
675 				dev_notice(udphy->dev, "trsv ln0 mon rx cdr lock timeout\n");  in udphy_status_check()
677 			ret = regmap_read_poll_timeout(udphy->pma_regmap,  in udphy_status_check()
682 				dev_notice(udphy->dev, "trsv ln2 mon rx cdr lock timeout\n");  in udphy_status_check()
689 static int udphy_init(struct rockchip_udphy *udphy)  in udphy_init()  argument
691 	const struct rockchip_udphy_cfg *cfg = udphy->cfgs;  in udphy_init()
695 	if (udphy->mode & UDPHY_MODE_USB)  in udphy_init()
696 		grfreg_write(udphy->udphygrf, &cfg->grfcfg.rx_lfps, true);  in udphy_init()
699 	grfreg_write(udphy->udphygrf, &cfg->grfcfg.low_pwrn, true);  in udphy_init()
701 	udphy_reset_deassert(udphy, "pma_apb");  in udphy_init()
702 	udphy_reset_deassert(udphy, "pcs_apb");  in udphy_init()
705 	ret = __regmap_multi_reg_write(udphy->pma_regmap, udphy_init_sequence,  in udphy_init()
708 		dev_err(udphy->dev, "init sequence set error %d\n", ret);  in udphy_init()
712 	ret = udphy_refclk_set(udphy);  in udphy_init()
714 		dev_err(udphy->dev, "refclk set error %d\n", ret);  in udphy_init()
719 	regmap_update_bits(udphy->pma_regmap, CMN_LANE_MUX_AND_EN_OFFSET,  in udphy_init()
721 			   FIELD_PREP(CMN_DP_LANE_MUX_N(3), udphy->lane_mux_sel[3]) |  in udphy_init()
722 			   FIELD_PREP(CMN_DP_LANE_MUX_N(2), udphy->lane_mux_sel[2]) |  in udphy_init()
723 			   FIELD_PREP(CMN_DP_LANE_MUX_N(1), udphy->lane_mux_sel[1]) |  in udphy_init()
724 			   FIELD_PREP(CMN_DP_LANE_MUX_N(0), udphy->lane_mux_sel[0]) |  in udphy_init()
728 	if (udphy->mode & UDPHY_MODE_USB)  in udphy_init()
729 		udphy_reset_deassert(udphy, "init");  in udphy_init()
731 	if (udphy->mode & UDPHY_MODE_DP) {  in udphy_init()
732 		regmap_update_bits(udphy->pma_regmap, CMN_DP_RSTN_OFFSET,  in udphy_init()
740 	if (udphy->mode & UDPHY_MODE_USB) {  in udphy_init()
741 		udphy_reset_deassert(udphy, "cmn");  in udphy_init()
742 		udphy_reset_deassert(udphy, "lane");  in udphy_init()
746 	ret = udphy_status_check(udphy);  in udphy_init()
753 	udphy_reset_assert(udphy, "init");  in udphy_init()
754 	udphy_reset_assert(udphy, "cmn");  in udphy_init()
755 	udphy_reset_assert(udphy, "lane");  in udphy_init()
758 	udphy_reset_assert(udphy, "pma_apb");  in udphy_init()
759 	udphy_reset_assert(udphy, "pcs_apb");  in udphy_init()
763 static int udphy_setup(struct rockchip_udphy *udphy)  in udphy_setup()  argument
767 	ret = udphy_init(udphy);  in udphy_setup()
769 		dev_err(udphy->dev, "failed to init combophy\n");  in udphy_setup()
774 static int udphy_disable(struct rockchip_udphy *udphy)  in udphy_disable()  argument
776 	const struct rockchip_udphy_cfg *cfg = udphy->cfgs;  in udphy_disable()
780 		reset_assert(&udphy->rsts[i]);  in udphy_disable()
785 static int udphy_parse_lane_mux_data(struct rockchip_udphy *udphy, struct udevice *dev)  in udphy_parse_lane_mux_data()  argument
793 		udphy->mode = UDPHY_MODE_USB;  in udphy_parse_lane_mux_data()
804 	ret = dev_read_u32_array(dev, "rockchip,dp-lane-mux", udphy->dp_lane_sel, num_lanes);  in udphy_parse_lane_mux_data()
813 		if (udphy->dp_lane_sel[i] > 3) {  in udphy_parse_lane_mux_data()
818 		udphy->lane_mux_sel[udphy->dp_lane_sel[i]] = PHY_LANE_MUX_DP;  in udphy_parse_lane_mux_data()
821 			if (udphy->dp_lane_sel[i] == udphy->dp_lane_sel[j]) {  in udphy_parse_lane_mux_data()
828 	udphy->mode = UDPHY_MODE_DP;  in udphy_parse_lane_mux_data()
830 		udphy->mode |= UDPHY_MODE_USB;  in udphy_parse_lane_mux_data()
831 		udphy->flip = udphy->lane_mux_sel[0] == PHY_LANE_MUX_DP ? true : false;  in udphy_parse_lane_mux_data()
837 static int udphy_parse_dt(struct rockchip_udphy *udphy, struct udevice *dev)  in udphy_parse_dt()  argument
842 	udphy->u2phygrf = syscon_regmap_lookup_by_phandle(dev, "rockchip,u2phy-grf");  in udphy_parse_dt()
843 	if (IS_ERR(udphy->u2phygrf)) {  in udphy_parse_dt()
844 		if (PTR_ERR(udphy->u2phygrf) == -ENODEV) {  in udphy_parse_dt()
846 			udphy->u2phygrf = NULL;  in udphy_parse_dt()
848 			return PTR_ERR(udphy->u2phygrf);  in udphy_parse_dt()
852 	udphy->udphygrf = syscon_regmap_lookup_by_phandle(dev, "rockchip,usbdpphy-grf");  in udphy_parse_dt()
853 	if (IS_ERR(udphy->udphygrf)) {  in udphy_parse_dt()
854 		if (PTR_ERR(udphy->udphygrf) == -ENODEV) {  in udphy_parse_dt()
856 			udphy->udphygrf = NULL;  in udphy_parse_dt()
858 			return PTR_ERR(udphy->udphygrf);  in udphy_parse_dt()
862 	udphy->usbgrf = syscon_regmap_lookup_by_phandle(dev, "rockchip,usb-grf");  in udphy_parse_dt()
863 	if (IS_ERR(udphy->usbgrf)) {  in udphy_parse_dt()
864 		if (PTR_ERR(udphy->usbgrf) == -ENODEV) {  in udphy_parse_dt()
866 			udphy->usbgrf = NULL;  in udphy_parse_dt()
868 			return PTR_ERR(udphy->usbgrf);  in udphy_parse_dt()
872 	udphy->vogrf = syscon_regmap_lookup_by_phandle(dev, "rockchip,vo-grf");  in udphy_parse_dt()
873 	if (IS_ERR(udphy->vogrf)) {  in udphy_parse_dt()
874 		if (PTR_ERR(udphy->vogrf) == -ENODEV) {  in udphy_parse_dt()
876 			udphy->vogrf = NULL;  in udphy_parse_dt()
878 			return PTR_ERR(udphy->vogrf);  in udphy_parse_dt()
882 	ret = udphy_parse_lane_mux_data(udphy, dev);  in udphy_parse_dt()
888 		udphy->hs = maximum_speed <= USB_SPEED_HIGH ? true : false;  in udphy_parse_dt()
891 	ret = udphy_clk_init(udphy, dev);  in udphy_parse_dt()
895 	ret = udphy_reset_init(udphy, dev);  in udphy_parse_dt()
902 static int udphy_power_on(struct rockchip_udphy *udphy, u8 mode)  in udphy_power_on()  argument
906 	if (!(udphy->mode & mode)) {  in udphy_power_on()
907 		printf("%s: mode 0x%02x is not support\n", udphy->dev->name,  in udphy_power_on()
912 	if (udphy->status == UDPHY_MODE_NONE) {  in udphy_power_on()
913 		udphy->mode_change = false;  in udphy_power_on()
914 		ret = udphy_setup(udphy);  in udphy_power_on()
918 		if (udphy->mode & UDPHY_MODE_USB)  in udphy_power_on()
919 			udphy_u3_port_disable(udphy, false);  in udphy_power_on()
920 	} else if (udphy->mode_change) {  in udphy_power_on()
921 		udphy->mode_change = false;  in udphy_power_on()
922 		udphy->status = UDPHY_MODE_NONE;  in udphy_power_on()
923 		if (udphy->mode == UDPHY_MODE_DP)  in udphy_power_on()
924 			udphy_u3_port_disable(udphy, true);  in udphy_power_on()
926 		ret = udphy_disable(udphy);  in udphy_power_on()
929 		ret = udphy_setup(udphy);  in udphy_power_on()
934 	udphy->status |= mode;  in udphy_power_on()
939 static int udphy_power_off(struct rockchip_udphy *udphy, u8 mode)  in udphy_power_off()  argument
943 	if (!(udphy->mode & mode)) {  in udphy_power_off()
944 		dev_info(udphy->dev, "mode 0x%02x is not support\n", mode);  in udphy_power_off()
948 	if (!udphy->status)  in udphy_power_off()
951 	udphy->status &= ~mode;  in udphy_power_off()
953 	if (udphy->status == UDPHY_MODE_NONE) {  in udphy_power_off()
954 		ret = udphy_disable(udphy);  in udphy_power_off()
965 	struct rockchip_udphy *udphy = dev_get_priv(parent);  in rockchip_dpphy_power_on()  local
968 	dp_lanes = udphy_dplane_get(udphy);  in rockchip_dpphy_power_on()
970 	phy->attrs.max_link_rate = udphy->max_link_rate;  in rockchip_dpphy_power_on()
972 	ret = udphy_power_on(udphy, UDPHY_MODE_DP);  in rockchip_dpphy_power_on()
976 	ret = udphy_dplane_enable(udphy, dp_lanes);  in rockchip_dpphy_power_on()
980 	return udphy_dplane_select(udphy);  in rockchip_dpphy_power_on()
986 	struct rockchip_udphy *udphy = dev_get_priv(parent);  in rockchip_dpphy_power_off()  local
989 	ret = udphy_dplane_enable(udphy, 0);  in rockchip_dpphy_power_off()
993 	return udphy_power_off(udphy, UDPHY_MODE_DP);  in rockchip_dpphy_power_off()
996 static int rockchip_dpphy_verify_config(struct rockchip_udphy *udphy,  in rockchip_dpphy_verify_config()  argument
1048 static int dp_phy_set_rate(struct rockchip_udphy *udphy,  in dp_phy_set_rate()  argument
1054 	regmap_update_bits(udphy->pma_regmap, CMN_DP_RSTN_OFFSET,  in dp_phy_set_rate()
1059 		udphy->bw = DP_BW_RBR;  in dp_phy_set_rate()
1062 		udphy->bw = DP_BW_HBR;  in dp_phy_set_rate()
1065 		udphy->bw = DP_BW_HBR2;  in dp_phy_set_rate()
1068 		udphy->bw = DP_BW_HBR3;  in dp_phy_set_rate()
1074 	regmap_update_bits(udphy->pma_regmap, CMN_DP_LINK_OFFSET, CMN_DP_TX_LINK_BW,  in dp_phy_set_rate()
1075 			   FIELD_PREP(CMN_DP_TX_LINK_BW, udphy->bw));  in dp_phy_set_rate()
1076 	regmap_update_bits(udphy->pma_regmap, CMN_SSC_EN_OFFSET, CMN_ROPLL_SSC_EN,  in dp_phy_set_rate()
1078 	regmap_update_bits(udphy->pma_regmap, CMN_DP_RSTN_OFFSET, CMN_DP_CMN_RSTN,  in dp_phy_set_rate()
1081 	ret = regmap_read_poll_timeout(udphy->pma_regmap, CMN_ANA_ROPLL_DONE_OFFSET, val,  in dp_phy_set_rate()
1093 static void dp_phy_set_voltage(struct rockchip_udphy *udphy, u8 bw,  in dp_phy_set_voltage()  argument
1098 	const struct rockchip_udphy_cfg *cfg = udphy->cfgs;  in dp_phy_set_voltage()
1103 	regmap_write(udphy->pma_regmap, 0x0810 + offset, val);  in dp_phy_set_voltage()
1106 	regmap_write(udphy->pma_regmap, 0x0814 + offset, val);  in dp_phy_set_voltage()
1109 	regmap_write(udphy->pma_regmap, 0x0818 + offset, val);  in dp_phy_set_voltage()
1112 	regmap_write(udphy->pma_regmap, 0x081c + offset, val);  in dp_phy_set_voltage()
1115 static int dp_phy_set_voltages(struct rockchip_udphy *udphy,  in dp_phy_set_voltages()  argument
1121 		lane = udphy->dp_lane_sel[i];  in dp_phy_set_voltages()
1125 			regmap_update_bits(udphy->pma_regmap, TRSV_ANA_TX_CLK_OFFSET_N(lane),  in dp_phy_set_voltages()
1128 						      udphy->lane_mux_sel[lane]));  in dp_phy_set_voltages()
1132 			regmap_update_bits(udphy->pma_regmap, TRSV_ANA_TX_CLK_OFFSET_N(lane),  in dp_phy_set_voltages()
1138 		dp_phy_set_voltage(udphy, udphy->bw, dp->voltage[i], dp->pre[i], lane);  in dp_phy_set_voltages()
1148 	struct rockchip_udphy *udphy = dev_get_priv(parent);  in rockchip_dpphy_configure()  local
1151 	ret = rockchip_dpphy_verify_config(udphy, &opts->dp);  in rockchip_dpphy_configure()
1156 		ret = dp_phy_set_rate(udphy, &opts->dp);  in rockchip_dpphy_configure()
1159 			       udphy->dev->name);  in rockchip_dpphy_configure()
1165 		ret = dp_phy_set_voltages(udphy, &opts->dp);  in rockchip_dpphy_configure()
1168 			       udphy->dev->name);  in rockchip_dpphy_configure()
1185 	struct rockchip_udphy *udphy = dev_get_priv(parent);  in rockchip_u3phy_init()  local
1188 	if (!(udphy->mode & UDPHY_MODE_USB) || udphy->hs) {  in rockchip_u3phy_init()
1189 		udphy_u3_port_disable(udphy, true);  in rockchip_u3phy_init()
1193 	return udphy_power_on(udphy, UDPHY_MODE_USB);  in rockchip_u3phy_init()
1199 	struct rockchip_udphy *udphy = dev_get_priv(parent);  in rockchip_u3phy_exit()  local
1202 	if (!(udphy->mode & UDPHY_MODE_USB) || udphy->hs)  in rockchip_u3phy_exit()
1205 	return udphy_power_off(udphy, UDPHY_MODE_USB);  in rockchip_u3phy_exit()
1219 	struct rockchip_udphy *udphy;  in rockchip_u3phy_uboot_init()  local
1242 	udphy = dev_get_priv(udev);  in rockchip_u3phy_uboot_init()
1243 	if (!(udphy->mode & UDPHY_MODE_USB) || udphy->hs) {  in rockchip_u3phy_uboot_init()
1248 	udphy->flip = false;  in rockchip_u3phy_uboot_init()
1249 	udphy_set_typec_default_mapping(udphy);  in rockchip_u3phy_uboot_init()
1251 	ret =  udphy_power_on(udphy, UDPHY_MODE_USB);  in rockchip_u3phy_uboot_init()
1257 	ret = regmap_read_poll_timeout(udphy->pma_regmap,  in rockchip_u3phy_uboot_init()
1269 	udphy_u3_port_disable(udphy, true);  in rockchip_u3phy_uboot_init()
1276 	struct rockchip_udphy *udphy = dev_get_priv(dev);  in rockchip_udphy_probe()  local
1280 	udphy->dev = dev;  in rockchip_udphy_probe()
1285 	udphy->id = id;  in rockchip_udphy_probe()
1292 	udphy->cfgs = phy_cfgs;  in rockchip_udphy_probe()
1294 	ret = regmap_init_mem(dev, &udphy->pma_regmap);  in rockchip_udphy_probe()
1297 	udphy->pma_regmap->base += UDPHY_PMA;  in rockchip_udphy_probe()
1299 	ret = udphy_parse_dt(udphy, dev);  in rockchip_udphy_probe()
1348 	struct rockchip_udphy *udphy = dev_get_priv(dev->parent);  in rockchip_dpphy_probe()  local
1364 	udphy->max_link_rate = max_link_rate;  in rockchip_dpphy_probe()