187 	u32 dp_lane_sel[4];  member
547 		value |= 2 << udphy->dp_lane_sel[2] * 2;  in udphy_dplane_select()
548 		value |= 3 << udphy->dp_lane_sel[3] * 2;  in udphy_dplane_select()
550 		value |= 0 << udphy->dp_lane_sel[0] * 2;  in udphy_dplane_select()
551 		value |= 1 << udphy->dp_lane_sel[1] * 2;  in udphy_dplane_select()
594 		val |= BIT(udphy->dp_lane_sel[i]);  in udphy_dplane_enable()
611 		udphy->dp_lane_sel[0] = 0;  in udphy_set_typec_default_mapping()
612 		udphy->dp_lane_sel[1] = 1;  in udphy_set_typec_default_mapping()
613 		udphy->dp_lane_sel[2] = 3;  in udphy_set_typec_default_mapping()
614 		udphy->dp_lane_sel[3] = 2;  in udphy_set_typec_default_mapping()
622 		udphy->dp_lane_sel[0] = 2;  in udphy_set_typec_default_mapping()
623 		udphy->dp_lane_sel[1] = 3;  in udphy_set_typec_default_mapping()
624 		udphy->dp_lane_sel[2] = 1;  in udphy_set_typec_default_mapping()
625 		udphy->dp_lane_sel[3] = 0;  in udphy_set_typec_default_mapping()
804 	ret = dev_read_u32_array(dev, "rockchip,dp-lane-mux", udphy->dp_lane_sel, num_lanes);  in udphy_parse_lane_mux_data()
813 		if (udphy->dp_lane_sel[i] > 3) {  in udphy_parse_lane_mux_data()
818 		udphy->lane_mux_sel[udphy->dp_lane_sel[i]] = PHY_LANE_MUX_DP;  in udphy_parse_lane_mux_data()
821 			if (udphy->dp_lane_sel[i] == udphy->dp_lane_sel[j]) {  in udphy_parse_lane_mux_data()
1121 		lane = udphy->dp_lane_sel[i];  in dp_phy_set_voltages()