244 static void afi_writel(struct tegra_pcie *pcie, unsigned long value,  in afi_writel()  argument
247 	writel(value, pcie->afi.start + offset);  in afi_writel()
255 static void pads_writel(struct tegra_pcie *pcie, unsigned long value,  in pads_writel()  argument
258 	writel(value, pcie->pads.start + offset);  in pads_writel()
274 static void rp_writel(struct tegra_pcie_port *port, unsigned long value,  in rp_writel()  argument
277 	writel(value, port->regs.start + offset);  in rp_writel()
320 	unsigned long address, value;  in pci_tegra_read_config()  local
325 		value = 0xffffffff;  in pci_tegra_read_config()
329 	value = readl(address);  in pci_tegra_read_config()
335 			value &= ~0x00ff0000;  in pci_tegra_read_config()
336 			value |= PCI_CLASS_BRIDGE_PCI << 16;  in pci_tegra_read_config()
342 	*valuep = pci_conv_32_to_size(value, offset, size);  in pci_tegra_read_config()
348 				  uint offset, ulong value,  in pci_tegra_write_config()  argument
361 	value = pci_conv_size_to_32(old, value, offset, size);  in pci_tegra_write_config()
362 	writel(value, address);  in pci_tegra_write_config()
613 	unsigned long value;  in tegra_pcie_power_on()  local
642 		value = readl(NV_PA_CLK_RST_BASE + 0x48c);  in tegra_pcie_power_on()
643 		value |= (1 << 0);  in tegra_pcie_power_on()
644 		value &= ~(1 << 1);  in tegra_pcie_power_on()
645 		writel(value, NV_PA_CLK_RST_BASE + 0x48c);  in tegra_pcie_power_on()
661 	u32 value;  in tegra_pcie_pll_wait()  local
664 		value = pads_readl(pcie, soc->pads_pll_ctl);  in tegra_pcie_pll_wait()
665 		if (value & PADS_PLL_CTL_LOCKDET)  in tegra_pcie_pll_wait()
675 	u32 value;  in tegra_pcie_phy_enable()  local
682 	value = pads_readl(pcie, PADS_CTL);  in tegra_pcie_phy_enable()
683 	value |= PADS_CTL_IDDQ_1L;  in tegra_pcie_phy_enable()
684 	pads_writel(pcie, value, PADS_CTL);  in tegra_pcie_phy_enable()
690 	value = pads_readl(pcie, soc->pads_pll_ctl);  in tegra_pcie_phy_enable()
691 	value &= ~(PADS_PLL_CTL_REFCLK_MASK | PADS_PLL_CTL_TXCLKREF_MASK);  in tegra_pcie_phy_enable()
692 	value |= PADS_PLL_CTL_REFCLK_INTERNAL_CML | soc->tx_ref_sel;  in tegra_pcie_phy_enable()
693 	pads_writel(pcie, value, soc->pads_pll_ctl);  in tegra_pcie_phy_enable()
696 	value = pads_readl(pcie, soc->pads_pll_ctl);  in tegra_pcie_phy_enable()
697 	value &= ~PADS_PLL_CTL_RST_B4SM;  in tegra_pcie_phy_enable()
698 	pads_writel(pcie, value, soc->pads_pll_ctl);  in tegra_pcie_phy_enable()
703 	value = pads_readl(pcie, soc->pads_pll_ctl);  in tegra_pcie_phy_enable()
704 	value |= PADS_PLL_CTL_RST_B4SM;  in tegra_pcie_phy_enable()
705 	pads_writel(pcie, value, soc->pads_pll_ctl);  in tegra_pcie_phy_enable()
715 	value = pads_readl(pcie, PADS_CTL);  in tegra_pcie_phy_enable()
716 	value &= ~PADS_CTL_IDDQ_1L;  in tegra_pcie_phy_enable()
717 	pads_writel(pcie, value, PADS_CTL);  in tegra_pcie_phy_enable()
720 	value = pads_readl(pcie, PADS_CTL);  in tegra_pcie_phy_enable()
721 	value |= PADS_CTL_TX_DATA_EN_1L | PADS_CTL_RX_DATA_EN_1L;  in tegra_pcie_phy_enable()
722 	pads_writel(pcie, value, PADS_CTL);  in tegra_pcie_phy_enable()
732 	u32 value;  local
740 		value = afi_readl(pcie, AFI_PLLE_CONTROL);
741 		value &= ~AFI_PLLE_CONTROL_BYPASS_PADS2PLLE_CONTROL;
742 		value |= AFI_PLLE_CONTROL_PADS2PLLE_CONTROL_EN;
743 		afi_writel(pcie, value, AFI_PLLE_CONTROL);
749 	value = afi_readl(pcie, AFI_PCIE_CONFIG);
750 	value &= ~AFI_PCIE_CONFIG_SM2TMS0_XBAR_CONFIG_MASK;
751 	value |= AFI_PCIE_CONFIG_PCIE_DISABLE_ALL | pcie->xbar;
754 		value &= ~AFI_PCIE_CONFIG_PCIE_DISABLE(port->index);
756 	afi_writel(pcie, value, AFI_PCIE_CONFIG);
758 	value = afi_readl(pcie, AFI_FUSE);
761 		value &= ~AFI_FUSE_PCIE_T0_GEN2_DIS;
763 		value |= AFI_FUSE_PCIE_T0_GEN2_DIS;
765 	afi_writel(pcie, value, AFI_FUSE);
791 	value = afi_readl(pcie, AFI_CONFIGURATION);
792 	value |= AFI_CONFIGURATION_EN_FPCI;
793 	afi_writel(pcie, value, AFI_CONFIGURATION);
899 	unsigned long value;  local
902 	value = afi_readl(port->pcie, ctrl);
903 	value &= ~AFI_PEX_CTRL_RST;
904 	afi_writel(port->pcie, value, ctrl);
908 	value = afi_readl(port->pcie, ctrl);
909 	value |= AFI_PEX_CTRL_RST;
910 	afi_writel(port->pcie, value, ctrl);
918 	unsigned long value;  local
921 	value = afi_readl(pcie, ctrl);
922 	value |= AFI_PEX_CTRL_REFCLK_EN;
925 		value |= AFI_PEX_CTRL_CLKREQ_EN;
927 	value |= AFI_PEX_CTRL_OVERRIDE_EN;
929 	afi_writel(pcie, value, ctrl);
934 		value = rp_readl(port, RP_VEND_CTL2);
935 		value |= RP_VEND_CTL2_PCA_ENABLE;
936 		rp_writel(port, value, RP_VEND_CTL2);
948 	unsigned long value;  local
950 	value = rp_readl(port, RP_PRIV_MISC);
951 	value &= ~RP_PRIV_MISC_PRSNT_MAP_EP_ABSNT;
952 	value |= RP_PRIV_MISC_PRSNT_MAP_EP_PRSNT;
953 	rp_writel(port, value, RP_PRIV_MISC);
959 			value = rp_readl(port, RP_VEND_XP);
960 			if (value & RP_VEND_XP_DL_UP)
974 			value = rp_readl(port, RP_LINK_CONTROL_STATUS);
975 			if (value & RP_LINK_CONTROL_STATUS_DL_LINK_ACTIVE)
991 	unsigned long value;  local
994 	value = afi_readl(port->pcie, ctrl);
995 	value &= ~AFI_PEX_CTRL_RST;
996 	afi_writel(port->pcie, value, ctrl);
999 	value = afi_readl(port->pcie, ctrl);
1000 	value &= ~AFI_PEX_CTRL_REFCLK_EN;
1001 	afi_writel(port->pcie, value, ctrl);