230 	const struct tegra_pcie_soc *soc;  member
612 	const struct tegra_pcie_soc *soc = pcie->soc;  in tegra_pcie_power_on()  local
640 	if (soc->has_cml_clk) {  in tegra_pcie_power_on()
659 	const struct tegra_pcie_soc *soc = pcie->soc;  in tegra_pcie_pll_wait()  local
664 		value = pads_readl(pcie, soc->pads_pll_ctl);  in tegra_pcie_pll_wait()
674 	const struct tegra_pcie_soc *soc = pcie->soc;  in tegra_pcie_phy_enable()  local
690 	value = pads_readl(pcie, soc->pads_pll_ctl);  in tegra_pcie_phy_enable()
692 	value |= PADS_PLL_CTL_REFCLK_INTERNAL_CML | soc->tx_ref_sel;  in tegra_pcie_phy_enable()
693 	pads_writel(pcie, value, soc->pads_pll_ctl);  in tegra_pcie_phy_enable()
696 	value = pads_readl(pcie, soc->pads_pll_ctl);  in tegra_pcie_phy_enable()
698 	pads_writel(pcie, value, soc->pads_pll_ctl);  in tegra_pcie_phy_enable()
703 	value = pads_readl(pcie, soc->pads_pll_ctl);  in tegra_pcie_phy_enable()
705 	pads_writel(pcie, value, soc->pads_pll_ctl);  in tegra_pcie_phy_enable()
730 	const struct tegra_pcie_soc *soc = pcie->soc;  local
746 	if (soc->has_pex_bias_ctrl)
760 	if (soc->has_gen2)
889 		ret = port->pcie->soc->afi_pex2_ctrl;
916 	const struct tegra_pcie_soc *soc = pcie->soc;  local
924 	if (pcie->soc->has_pex_clkreq_en)
933 	if (soc->force_pca_enable) {
940 	pads_writel(pcie, soc->pads_refclk_cfg0, PADS_REFCLK_CFG0);
941 	if (soc->num_ports > 2)
942 		pads_writel(pcie, soc->pads_refclk_cfg1, PADS_REFCLK_CFG1);
1093 	pcie->soc = &pci_tegra_soc[id];