49 				u64 size)  in set_inbound_window()
85 					 u64 out_lo, u8 pcie_cap,  in fsl_pci_setup_inbound_windows()
89 	u64 sz = min((u64)gd->ram_size, (1ull << 32));  in fsl_pci_setup_inbound_windows()
114 			(u64)bus_start, (u64)phys_start, (u64)sz);  in fsl_pci_setup_inbound_windows()
130 			(u64)bus_start, (u64)phys_start, (u64)pci_sz);  in fsl_pci_setup_inbound_windows()
143 				(u64)bus_start, (u64)phys_start, (u64)pci_sz);  in fsl_pci_setup_inbound_windows()
164 		(u64)CONFIG_SYS_PCI64_MEMORY_BUS,  in fsl_pci_setup_inbound_windows()
165 		(u64)CONFIG_SYS_PCI_MEMORY_PHYS,  in fsl_pci_setup_inbound_windows()
166 		(u64)pci_sz);  in fsl_pci_setup_inbound_windows()
178 			(u64)bus_start, (u64)phys_start, (u64)pci_sz);  in fsl_pci_setup_inbound_windows()
190 	if (sz && (((u64)gd->ram_size) < (1ull << 32)))  in fsl_pci_setup_inbound_windows()
206 			(u64)CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_PHYS,  in fsl_pcie_boot_master()
207 			(u64)CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS1,  in fsl_pcie_boot_master()
224 			(u64)CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_PHYS,  in fsl_pcie_boot_master()
225 			(u64)CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS2,  in fsl_pcie_boot_master()
240 			(u64)CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_PHYS,  in fsl_pcie_boot_master()
241 			(u64)CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_BUS,  in fsl_pcie_boot_master()
320 	u64 out_hi = 0, out_lo = -1ULL;  in fsl_pci_init()
335 		u32 sz = (__ilog2_u64((u64)hose->regions[r].size) - 1);  in fsl_pci_init()
339 			u64 start = hose->regions[r].bus_start;  in fsl_pci_init()
340 			u64 end = start + hose->regions[r].size;  in fsl_pci_init()
375 	out_lo = min(out_lo, (u64)pcicsrbar);  in fsl_pci_init()
413 			(u64)hose->regions[r].phys_start,  in fsl_pci_init()
414 			(u64)hose->regions[r].bus_start,  in fsl_pci_init()
415 			(u64)hose->regions[r].size,  in fsl_pci_init()