51 	u32 sz = (__ilog2_u64(size) - 1);  in set_inbound_window()  local
69 	out_be32(&pi->piwar, flag | sz);  in set_inbound_window()
89 	u64 sz = min((u64)gd->ram_size, (1ull << 32));  in fsl_pci_setup_inbound_windows()  local
102 	if ((bus_start + sz) > out_lo) {  in fsl_pci_setup_inbound_windows()
103 		sz = out_lo - bus_start;  in fsl_pci_setup_inbound_windows()
104 		debug ("limiting size to %llx\n", sz);  in fsl_pci_setup_inbound_windows()
107 	pci_sz = 1ull << __ilog2_u64(sz);  in fsl_pci_setup_inbound_windows()
112 	if ((pcie_cap == PCI_CAP_ID_EXP) && (pci_sz < sz)) {  in fsl_pci_setup_inbound_windows()
114 			(u64)bus_start, (u64)phys_start, (u64)sz);  in fsl_pci_setup_inbound_windows()
115 		pci_set_region(r, bus_start, phys_start, sz,  in fsl_pci_setup_inbound_windows()
123 		if (pci_sz != sz)  in fsl_pci_setup_inbound_windows()
124 			sz = 2ull << __ilog2_u64(sz);  in fsl_pci_setup_inbound_windows()
126 		set_inbound_window(pi--, r++, sz);  in fsl_pci_setup_inbound_windows()
127 		sz = 0; /* make sure we dont set the R2 window */  in fsl_pci_setup_inbound_windows()
136 		sz -= pci_sz;  in fsl_pci_setup_inbound_windows()
140 		pci_sz = 1ull << __ilog2_u64(sz);  in fsl_pci_setup_inbound_windows()
141 		if (sz) {  in fsl_pci_setup_inbound_windows()
148 			sz -= pci_sz;  in fsl_pci_setup_inbound_windows()
175 	pci_sz = 1ull << __ilog2_u64(sz);  in fsl_pci_setup_inbound_windows()
176 	if (sz) {  in fsl_pci_setup_inbound_windows()
182 		sz -= pci_sz;  in fsl_pci_setup_inbound_windows()
190 	if (sz && (((u64)gd->ram_size) < (1ull << 32)))  in fsl_pci_setup_inbound_windows()
192 			"inbound windows -- %lld remaining\n", sz);  in fsl_pci_setup_inbound_windows()
335 		u32 sz = (__ilog2_u64((u64)hose->regions[r].size) - 1);  in fsl_pci_init()  local
350 				out_be32(&po->powar, POWAR_EN | sz |  in fsl_pci_init()
353 				out_be32(&po->powar, POWAR_EN | sz |  in fsl_pci_init()