81 #define SROM_CLK_WRITE(data, ioaddr) do {			\  argument
82 	outl(data|CR9_SROM_READ|CR9_SRCS, ioaddr);		\
84 	outl(data|CR9_SROM_READ|CR9_SRCS|CR9_SRCLK, ioaddr);	\
86 	outl(data|CR9_SROM_READ|CR9_SRCS, ioaddr);		\
108 	long ioaddr;			/* I/O base address */  member
242 		db->ioaddr = dev->iobase;  in uli526x_initialize()
295 		__FUNCTION__, db->ioaddr);  in uli526x_init_one()
310 		((u16 *) db->srom)[i] = cpu_to_le16(read_srom_word(db->ioaddr,  in uli526x_init_one()
343 	if (!((inl(db->ioaddr + DCR12)) & 0x8)) {  in uli526x_disable()
345 		outl(ULI526X_RESET, db->ioaddr + DCR0);  in uli526x_disable()
347 		uli_phy_write(db->ioaddr, db->phy_addr, 0, 0x8000, db->chip_id);  in uli526x_disable()
373 	outl(ULI526X_RESET, db->ioaddr + DCR0);	/* RESET MAC */  in uli526x_init()
375 	outl(db->cr0_data, db->ioaddr + DCR0);  in uli526x_init()
383 		phy_value = uli_phy_read(db->ioaddr, phy_tmp, 3, db->chip_id);  in uli526x_init()
391 	printf("%s(): db->ioaddr= 0x%x\n", __FUNCTION__, db->ioaddr);  in uli526x_init()
400 	if (!(inl(db->ioaddr + DCR12) & 0x8)) {  in uli526x_init()
402 		phy_reg_reset = uli_phy_read(db->ioaddr,  in uli526x_init()
405 		uli_phy_write(db->ioaddr, db->phy_addr, 0,  in uli526x_init()
417 	uli526x_descriptor_init(db, db->ioaddr);  in uli526x_init()
420 	update_cr6(db->cr6_data, db->ioaddr);  in uli526x_init()
424 	outl(db->cr7_data, db->ioaddr + DCR7);  in uli526x_init()
427 	outl(db->cr15_data, db->ioaddr + DCR15);  in uli526x_init()
431 	update_cr6(db->cr6_data, db->ioaddr);  in uli526x_init()
432 	while (!(inl(db->ioaddr + DCR12) & 0x8))  in uli526x_init()
477 	db->cr5_data = inl(db->ioaddr + DCR5);  in uli526x_start_xmit()
478 	outl(db->cr5_data, db->ioaddr + DCR5);  in uli526x_start_xmit()
521 							db->ioaddr);  in uli526x_free_tx_pkt()
625 	unsigned long ioaddr)  in uli526x_descriptor_init()  argument
637 	outl(db->first_tx_desc_dma, ioaddr + DCR4);     /* TX DESC address */  in uli526x_descriptor_init()
645 	outl(db->first_rx_desc_dma, ioaddr + DCR3);	/* RX DESC address */  in uli526x_descriptor_init()
693 static void update_cr6(u32 cr6_data, unsigned long ioaddr)  in update_cr6()  argument
696 	outl(cr6_data, ioaddr + DCR6);  in update_cr6()
733 static u16 read_srom_word(long ioaddr, int offset)  in read_srom_word()  argument
737 	long cr9_ioaddr = ioaddr + DCR9;  in read_srom_word()
779 	phy_reg = uli_phy_read(db->ioaddr,  in uli526x_set_phyxcer()
801 	uli_phy_write(db->ioaddr, db->phy_addr, 4, phy_reg, db->chip_id);  in uli526x_set_phyxcer()
804 	uli_phy_write(db->ioaddr, db->phy_addr, 0, 0x1200, db->chip_id);  in uli526x_set_phyxcer()
816 	unsigned long ioaddr;  in uli_phy_write()  local
823 	ioaddr = iobase + DCR9;  in uli_phy_write()
827 		phy_write_1bit(ioaddr, PHY_DATA_1, chip_id);  in uli_phy_write()
830 	phy_write_1bit(ioaddr, PHY_DATA_0, chip_id);  in uli_phy_write()
831 	phy_write_1bit(ioaddr, PHY_DATA_1, chip_id);  in uli_phy_write()
834 	phy_write_1bit(ioaddr, PHY_DATA_0, chip_id);  in uli_phy_write()
835 	phy_write_1bit(ioaddr, PHY_DATA_1, chip_id);  in uli_phy_write()
839 		phy_write_1bit(ioaddr, phy_addr & i ?  in uli_phy_write()
844 		phy_write_1bit(ioaddr, offset & i ?  in uli_phy_write()
848 	phy_write_1bit(ioaddr, PHY_DATA_1, chip_id);  in uli_phy_write()
849 	phy_write_1bit(ioaddr, PHY_DATA_0, chip_id);  in uli_phy_write()
853 		phy_write_1bit(ioaddr, phy_data & i ?  in uli_phy_write()
866 	unsigned long ioaddr;  in uli_phy_read()  local
871 	ioaddr = iobase + DCR9;  in uli_phy_read()
875 		phy_write_1bit(ioaddr, PHY_DATA_1, chip_id);  in uli_phy_read()
878 	phy_write_1bit(ioaddr, PHY_DATA_0, chip_id);  in uli_phy_read()
879 	phy_write_1bit(ioaddr, PHY_DATA_1, chip_id);  in uli_phy_read()
882 	phy_write_1bit(ioaddr, PHY_DATA_1, chip_id);  in uli_phy_read()
883 	phy_write_1bit(ioaddr, PHY_DATA_0, chip_id);  in uli_phy_read()
887 		phy_write_1bit(ioaddr, phy_addr & i ?  in uli_phy_read()
892 		phy_write_1bit(ioaddr, offset & i ?  in uli_phy_read()
896 	phy_read_1bit(ioaddr, chip_id);  in uli_phy_read()
901 		phy_data |= phy_read_1bit(ioaddr, chip_id);  in uli_phy_read()
909 	unsigned long ioaddr, cr10_value;  in phy_readby_cr10()  local
911 	ioaddr = iobase + DCR10;  in phy_readby_cr10()
915 	outl(cr10_value, ioaddr);  in phy_readby_cr10()
918 		cr10_value = inl(ioaddr);  in phy_readby_cr10()
928 	unsigned long ioaddr, cr10_value;  in phy_writeby_cr10()  local
930 	ioaddr = iobase + DCR10;  in phy_writeby_cr10()
934 	outl(cr10_value, ioaddr);  in phy_writeby_cr10()
941 static void phy_write_1bit(unsigned long ioaddr, u32 phy_data, u32 chip_id)  in phy_write_1bit()  argument
943 	outl(phy_data , ioaddr);			/* MII Clock Low */  in phy_write_1bit()
945 	outl(phy_data  | MDCLKH, ioaddr);	/* MII Clock High */  in phy_write_1bit()
947 	outl(phy_data , ioaddr);			/* MII Clock Low */  in phy_write_1bit()
955 static u16 phy_read_1bit(unsigned long ioaddr, u32 chip_id)  in phy_read_1bit()  argument
959 	outl(0x50000 , ioaddr);  in phy_read_1bit()
961 	phy_data = (inl(ioaddr) >> 19) & 0x1;  in phy_read_1bit()
962 	outl(0x40000 , ioaddr);  in phy_read_1bit()
977 	outl(0x10000, db->ioaddr + DCR0);	/* Diagnosis mode */  in set_mac_addr()
979 	outl(0x1c0, db->ioaddr + DCR13);  in set_mac_addr()
980 	outl(0, db->ioaddr + DCR14);	/* Clear reset port */  in set_mac_addr()
981 	outl(0x10, db->ioaddr + DCR14);	/* Reset ID Table pointer */  in set_mac_addr()
982 	outl(0, db->ioaddr + DCR14);	/* Clear reset port */  in set_mac_addr()
983 	outl(0, db->ioaddr + DCR13);	/* Clear CR13 */  in set_mac_addr()
985 	outl(0x1b0, db->ioaddr + DCR13);  in set_mac_addr()
989 		outl(addr, db->ioaddr + DCR14);  in set_mac_addr()
992 	outl(0, db->ioaddr + DCR13);	/* Clear CR13 */  in set_mac_addr()
993 	outl(0, db->ioaddr + DCR0);	/* Clear CR0 */  in set_mac_addr()