1421 	int i;  in mvpp2_prs_hw_write()  local
1431 	for (i = 0; i < MVPP2_PRS_TCAM_WORDS; i++)  in mvpp2_prs_hw_write()
1432 		mvpp2_write(priv, MVPP2_PRS_TCAM_DATA_REG(i), pe->tcam.word[i]);  in mvpp2_prs_hw_write()
1436 	for (i = 0; i < MVPP2_PRS_SRAM_WORDS; i++)  in mvpp2_prs_hw_write()
1437 		mvpp2_write(priv, MVPP2_PRS_SRAM_DATA_REG(i), pe->sram.word[i]);  in mvpp2_prs_hw_write()
1445 	int i;  in mvpp2_prs_hw_read()  local
1458 	for (i = 0; i < MVPP2_PRS_TCAM_WORDS; i++)  in mvpp2_prs_hw_read()
1459 		pe->tcam.word[i] = mvpp2_read(priv, MVPP2_PRS_TCAM_DATA_REG(i));  in mvpp2_prs_hw_read()
1463 	for (i = 0; i < MVPP2_PRS_SRAM_WORDS; i++)  in mvpp2_prs_hw_read()
1464 		pe->sram.word[i] = mvpp2_read(priv, MVPP2_PRS_SRAM_DATA_REG(i));  in mvpp2_prs_hw_read()
1578 	unsigned int i;  in mvpp2_prs_sram_ri_update()  local
1580 	for (i = 0; i < MVPP2_PRS_SRAM_RI_CTRL_BITS; i++) {  in mvpp2_prs_sram_ri_update()
1583 		if (!(mask & BIT(i)))  in mvpp2_prs_sram_ri_update()
1586 		if (bits & BIT(i))  in mvpp2_prs_sram_ri_update()
1587 			mvpp2_prs_sram_bits_set(pe, ri_off + i, 1);  in mvpp2_prs_sram_ri_update()
1589 			mvpp2_prs_sram_bits_clear(pe, ri_off + i, 1);  in mvpp2_prs_sram_ri_update()
1591 		mvpp2_prs_sram_bits_set(pe, MVPP2_PRS_SRAM_RI_CTRL_OFFS + i, 1);  in mvpp2_prs_sram_ri_update()
1599 	unsigned int i;  in mvpp2_prs_sram_ai_update()  local
1602 	for (i = 0; i < MVPP2_PRS_SRAM_AI_CTRL_BITS; i++) {  in mvpp2_prs_sram_ai_update()
1604 		if (!(mask & BIT(i)))  in mvpp2_prs_sram_ai_update()
1607 		if (bits & BIT(i))  in mvpp2_prs_sram_ai_update()
1608 			mvpp2_prs_sram_bits_set(pe, ai_off + i, 1);  in mvpp2_prs_sram_ai_update()
1610 			mvpp2_prs_sram_bits_clear(pe, ai_off + i, 1);  in mvpp2_prs_sram_ai_update()
1612 		mvpp2_prs_sram_bits_set(pe, MVPP2_PRS_SRAM_AI_CTRL_OFFS + i, 1);  in mvpp2_prs_sram_ai_update()
2225 	int err, index, i;  in mvpp2_prs_default_init()  local
2233 		for (i = 0; i < MVPP2_PRS_TCAM_WORDS; i++)  in mvpp2_prs_default_init()
2234 			mvpp2_write(priv, MVPP2_PRS_TCAM_DATA_REG(i), 0);  in mvpp2_prs_default_init()
2237 		for (i = 0; i < MVPP2_PRS_SRAM_WORDS; i++)  in mvpp2_prs_default_init()
2238 			mvpp2_write(priv, MVPP2_PRS_SRAM_DATA_REG(i), 0);  in mvpp2_prs_default_init()
2634 	int i;  in mvpp2_bm_bufs_free()  local
2636 	for (i = 0; i < bm_pool->buf_num; i++) {  in mvpp2_bm_bufs_free()
2667 	int i, err, size;  in mvpp2_bm_pools_init()  local
2672 	for (i = 0; i < MVPP2_BM_POOLS_NUM; i++) {  in mvpp2_bm_pools_init()
2673 		bm_pool = &priv->bm_pools[i];  in mvpp2_bm_pools_init()
2674 		bm_pool->id = i;  in mvpp2_bm_pools_init()
2683 	dev_err(&pdev->dev, "failed to create BM pool %d, size %d\n", i, size);  in mvpp2_bm_pools_init()
2684 	for (i = i - 1; i >= 0; i--)  in mvpp2_bm_pools_init()
2685 		mvpp2_bm_pool_destroy(dev, priv, &priv->bm_pools[i]);  in mvpp2_bm_pools_init()
2691 	int i, err;  in mvpp2_bm_init()  local
2693 	for (i = 0; i < MVPP2_BM_POOLS_NUM; i++) {  in mvpp2_bm_init()
2695 		mvpp2_write(priv, MVPP2_BM_INTR_MASK_REG(i), 0);  in mvpp2_bm_init()
2697 		mvpp2_write(priv, MVPP2_BM_INTR_CAUSE_REG(i), 0);  in mvpp2_bm_init()
2793 	int i;  in mvpp2_bm_bufs_add()  local
2803 	for (i = 0; i < buf_num; i++) {  in mvpp2_bm_bufs_add()
2805 				  (dma_addr_t)buffer_loc.rx_buffer[i],  in mvpp2_bm_bufs_add()
2806 				  (unsigned long)buffer_loc.rx_buffer[i]);  in mvpp2_bm_bufs_add()
2811 	bm_pool->buf_num += i;  in mvpp2_bm_bufs_add()
2813 	return i;  in mvpp2_bm_bufs_add()
4034 	int i;  in mvpp2_txq_bufs_free()  local
4036 	for (i = 0; i < num; i++)  in mvpp2_txq_bufs_free()
4143 	int rx_received, i;  in mvpp2_rxq_drop_pkts()  local
4149 	for (i = 0; i < rx_received; i++) {  in mvpp2_rxq_drop_pkts()
4850 	int i;  in mvpp2_conf_mbus_windows()  local
4852 	for (i = 0; i < 6; i++) {  in mvpp2_conf_mbus_windows()
4853 		mvpp2_write(priv, MVPP2_WIN_BASE(i), 0);  in mvpp2_conf_mbus_windows()
4854 		mvpp2_write(priv, MVPP2_WIN_SIZE(i), 0);  in mvpp2_conf_mbus_windows()
4856 		if (i < 4)  in mvpp2_conf_mbus_windows()
4857 			mvpp2_write(priv, MVPP2_WIN_REMAP(i), 0);  in mvpp2_conf_mbus_windows()
4862 	for (i = 0; i < dram->num_cs; i++) {  in mvpp2_conf_mbus_windows()
4863 		const struct mbus_dram_window *cs = dram->cs + i;  in mvpp2_conf_mbus_windows()
4865 		mvpp2_write(priv, MVPP2_WIN_BASE(i),  in mvpp2_conf_mbus_windows()
4869 		mvpp2_write(priv, MVPP2_WIN_SIZE(i),  in mvpp2_conf_mbus_windows()
4872 		win_enable |= (1 << i);  in mvpp2_conf_mbus_windows()
4996 	int err, i;  in mvpp2_init()  local
5034 	for_each_present_cpu(i) {  in mvpp2_init()
5035 		priv->aggr_txqs[i].id = i;  in mvpp2_init()
5036 		priv->aggr_txqs[i].size = MVPP2_AGGR_TXQ_SIZE;  in mvpp2_init()
5037 		err = mvpp2_aggr_txq_init(dev, &priv->aggr_txqs[i],  in mvpp2_init()
5038 					  MVPP2_AGGR_TXQ_SIZE, i, priv);  in mvpp2_init()
5357 	int i;  in mvpp2_base_probe()  local
5386 	for (i = 0; i < MVPP2_BM_POOLS_NUM; i++) {  in mvpp2_base_probe()
5387 		buffer_loc.bm_pool[i] =  in mvpp2_base_probe()
5395 	for (i = 0; i < MVPP2_BM_LONG_BUF_NUM; i++) {  in mvpp2_base_probe()
5396 		buffer_loc.rx_buffer[i] =  in mvpp2_base_probe()
5529 	int i;  in mvpp2_remove()  local
5536 	for (i = 0; i < MVPP2_BM_POOLS_NUM; i++)  in mvpp2_remove()
5537 		mvpp2_bm_pool_destroy(dev, priv, &priv->bm_pools[i]);  in mvpp2_remove()