44 	int i = 0;  in dtsec_configure_serdes()  local
55 	memac_mdio_write(&bus, i, MDIO_DEVAD_NONE, 0x14, value);  in dtsec_configure_serdes()
59 	memac_mdio_write(&bus, i, MDIO_DEVAD_NONE, 0x4, value);  in dtsec_configure_serdes()
66 		memac_mdio_write(&bus, i, MDIO_DEVAD_NONE, 0x13, 0x0007);  in dtsec_configure_serdes()
67 		memac_mdio_write(&bus, i, MDIO_DEVAD_NONE, 0x12, 0xa120);  in dtsec_configure_serdes()
73 		memac_mdio_write(&bus, i, MDIO_DEVAD_NONE, 0x13, 0x0003);  in dtsec_configure_serdes()
74 		memac_mdio_write(&bus, i, MDIO_DEVAD_NONE, 0x12, 0x0d40);  in dtsec_configure_serdes()
79 	memac_mdio_write(&bus, i, MDIO_DEVAD_NONE, 0, value);  in dtsec_configure_serdes()
81 	if ((priv->enet_if == PHY_INTERFACE_MODE_QSGMII) && (i < 3)) {  in dtsec_configure_serdes()
82 		i++;  in dtsec_configure_serdes()
229 	int i;  in fm_eth_rx_port_parameter_init()  local
277 	for (i = 0; i < RX_BD_RING_SIZE; i++) {  in fm_eth_rx_port_parameter_init()
281 					i * MAX_RXBUF_LEN));  in fm_eth_rx_port_parameter_init()
283 					i * MAX_RXBUF_LEN));  in fm_eth_rx_port_parameter_init()
316 	int i;  in fm_eth_tx_port_parameter_init()  local
350 	for (i = 0; i < TX_BD_RING_SIZE; i++) {  in fm_eth_tx_port_parameter_init()
521 	int i;  in fm_eth_send()  local
528 	for (i = 0; muram_readw(&txbd->status) & TxBD_READY; i++) {  in fm_eth_send()
530 		if (i > 0x1000) {  in fm_eth_send()
553 	for (i = 0; muram_readw(&txbd->status) & TxBD_READY; i++) {  in fm_eth_send()
555 		if (i > 0x10000) {  in fm_eth_send()
734 	int i, num = info->num;  in fm_eth_initialize()  local
791 	for (i = 0; i < 6; i++)  in fm_eth_initialize()
792 		dev->enetaddr[i] = 0;  in fm_eth_initialize()