Lines Matching refs:bus
144 struct mii_dev *bus; member
155 static int ag7xxx_switch_read(struct mii_dev *bus, int addr, int reg, u16 *val) in ag7xxx_switch_read() argument
157 struct ar7xxx_eth_priv *priv = bus->priv; in ag7xxx_switch_read()
178 static int ag7xxx_switch_write(struct mii_dev *bus, int addr, int reg, u16 val) in ag7xxx_switch_write() argument
180 struct ar7xxx_eth_priv *priv = bus->priv; in ag7xxx_switch_write()
194 static int ag7xxx_switch_reg_read(struct mii_dev *bus, int reg, u32 *val) in ag7xxx_switch_reg_read() argument
196 struct ar7xxx_eth_priv *priv = bus->priv; in ag7xxx_switch_reg_read()
213 ret = ag7xxx_switch_write(bus, phy_addr, reg_addr, reg >> 9); in ag7xxx_switch_reg_read()
221 ret = ag7xxx_switch_read(bus, phy_temp, reg_temp | 0, &rv); in ag7xxx_switch_reg_read()
226 ret = ag7xxx_switch_read(bus, phy_temp, reg_temp | 1, &rv); in ag7xxx_switch_reg_read()
234 static int ag7xxx_switch_reg_write(struct mii_dev *bus, int reg, u32 val) in ag7xxx_switch_reg_write() argument
236 struct ar7xxx_eth_priv *priv = bus->priv; in ag7xxx_switch_reg_write()
252 ret = ag7xxx_switch_write(bus, phy_addr, reg_addr, reg >> 9); in ag7xxx_switch_reg_write()
268 ret = ag7xxx_switch_write(bus, phy_temp, reg_temp | 0, val & 0xffff); in ag7xxx_switch_reg_write()
272 ret = ag7xxx_switch_write(bus, phy_temp, reg_temp | 1, val >> 16); in ag7xxx_switch_reg_write()
276 ret = ag7xxx_switch_write(bus, phy_temp, reg_temp | 1, val >> 16); in ag7xxx_switch_reg_write()
280 ret = ag7xxx_switch_write(bus, phy_temp, reg_temp | 0, val & 0xffff); in ag7xxx_switch_reg_write()
288 static int ag7xxx_mdio_rw(struct mii_dev *bus, int addr, int reg, u32 val) in ag7xxx_mdio_rw() argument
297 ret = ag7xxx_switch_reg_read(bus, 0x98, &data); in ag7xxx_mdio_rw()
301 ret = ag7xxx_switch_reg_write(bus, 0x98, data); in ag7xxx_mdio_rw()
309 ret = ag7xxx_switch_reg_read(bus, 0x98, &data); in ag7xxx_mdio_rw()
320 static int ag7xxx_mdio_read(struct mii_dev *bus, int addr, int devad, int reg) in ag7xxx_mdio_read() argument
322 return ag7xxx_mdio_rw(bus, addr, reg, BIT(27)); in ag7xxx_mdio_read()
325 static int ag7xxx_mdio_write(struct mii_dev *bus, int addr, int devad, int reg, in ag7xxx_mdio_write() argument
330 ret = ag7xxx_mdio_rw(bus, addr, reg, val); in ag7xxx_mdio_write()
615 ret = ag7xxx_switch_reg_read(priv->bus, 0x10c, ®); in ag7xxx_mii_setup()
633 return ag7xxx_mdio_write(priv->bus, 4, 0, MII_BMCR, 0x9000); in ag933x_phy_setup_wan()
643 ret = ag7xxx_switch_reg_read(priv->bus, 0, ®); in ag933x_phy_setup_lan()
647 ret = ag7xxx_switch_reg_write(priv->bus, 0, reg); in ag933x_phy_setup_lan()
652 ret = ag7xxx_switch_reg_read(priv->bus, 0, ®); in ag933x_phy_setup_lan()
659 ret = ag7xxx_mdio_write(priv->bus, 0x4, 0, MII_BMCR, 0x9000); in ag933x_phy_setup_lan()
665 ret = ag7xxx_switch_reg_write(priv->bus, 0x78, BIT(8)); in ag933x_phy_setup_lan()
670 ret = ag7xxx_switch_reg_write(priv->bus, i * 0x100, BIT(9)); in ag933x_phy_setup_lan()
676 ret = ag7xxx_switch_reg_write(priv->bus, 0x38, 0xc000050e); in ag933x_phy_setup_lan()
681 ret = ag7xxx_switch_reg_write(priv->bus, 0x104, 0x4004); in ag933x_phy_setup_lan()
686 ret = ag7xxx_switch_reg_write(priv->bus, 0x70, 0xfa50); in ag933x_phy_setup_lan()
691 ret = ag7xxx_switch_reg_read(priv->bus, 0x5c, ®); in ag933x_phy_setup_lan()
695 ret = ag7xxx_switch_reg_write(priv->bus, 0x5c, reg); in ag933x_phy_setup_lan()
707 ret = ag7xxx_mdio_write(priv->bus, port, 0, MII_ADVERTISE, in ag933x_phy_setup_reset_set()
714 ret = ag7xxx_mdio_write(priv->bus, port, 0, MII_CTRL1000, in ag933x_phy_setup_reset_set()
720 return ag7xxx_mdio_write(priv->bus, port, 0, MII_BMCR, in ag933x_phy_setup_reset_set()
730 ret = ag7xxx_mdio_read(priv->bus, port, 0, MII_BMCR); in ag933x_phy_setup_reset_fin()
761 ret = ag7xxx_mdio_read(priv->bus, phymax, 0, MII_MIPSCR); in ag933x_phy_setup_common()
783 ret = ag7xxx_mdio_read(priv->bus, i, 0, MII_MIPSCR); in ag933x_phy_setup_common()
797 ret = ag7xxx_switch_reg_write(priv->bus, 0x624, 0x7f7f7f7f); in ag934x_phy_setup()
800 ret = ag7xxx_switch_reg_write(priv->bus, 0x10, 0x40000000); in ag934x_phy_setup()
803 ret = ag7xxx_switch_reg_write(priv->bus, 0x4, 0x07600000); in ag934x_phy_setup()
806 ret = ag7xxx_switch_reg_write(priv->bus, 0xc, 0x01000000); in ag934x_phy_setup()
809 ret = ag7xxx_switch_reg_write(priv->bus, 0x7c, 0x0000007e); in ag934x_phy_setup()
814 ret = ag7xxx_switch_reg_read(priv->bus, 0, ®); in ag934x_phy_setup()
819 ret = ag7xxx_mdio_write(priv->bus, i, 0, 0x1d, 0x0); in ag934x_phy_setup()
822 ret = ag7xxx_mdio_write(priv->bus, i, 0, 0x1e, 0x02ea); in ag934x_phy_setup()
825 ret = ag7xxx_mdio_write(priv->bus, i, 0, 0x1d, 0x3d); in ag934x_phy_setup()
828 ret = ag7xxx_mdio_write(priv->bus, i, 0, 0x1e, 0x68a0); in ag934x_phy_setup()
834 ret = ag7xxx_switch_reg_read(priv->bus, 0x66c, ®); in ag934x_phy_setup()
838 ret = ag7xxx_switch_reg_write(priv->bus, 0x66c, reg); in ag934x_phy_setup()
877 struct mii_dev *bus = mdio_alloc(); in ag7xxx_mdio_probe() local
879 if (!bus) in ag7xxx_mdio_probe()
882 bus->read = ag7xxx_mdio_read; in ag7xxx_mdio_probe()
883 bus->write = ag7xxx_mdio_write; in ag7xxx_mdio_probe()
884 snprintf(bus->name, sizeof(bus->name), dev->name); in ag7xxx_mdio_probe()
886 bus->priv = (void *)priv; in ag7xxx_mdio_probe()
888 return mdio_register(bus); in ag7xxx_mdio_probe()
945 priv->bus = miiphy_get_dev_by_name(dev->name); in ag7xxx_eth_probe()
958 mdio_unregister(priv->bus); in ag7xxx_eth_remove()
959 mdio_free(priv->bus); in ag7xxx_eth_remove()