Lines Matching refs:lbc
160 fsl_lbc_t *lbc = ctrl->regs; in set_addr() local
166 out_be32(&lbc->fbar, page_addr >> 6); in set_addr()
167 out_be32(&lbc->fpar, in set_addr()
172 out_be32(&lbc->fbar, page_addr >> 5); in set_addr()
173 out_be32(&lbc->fpar, in set_addr()
200 fsl_lbc_t *lbc = ctrl->regs; in fsl_elbc_run_command() local
206 out_be32(&lbc->fmr, priv->fmr | 3); in fsl_elbc_run_command()
208 out_be32(&lbc->mdr, ctrl->mdr); in fsl_elbc_run_command()
211 in_be32(&lbc->fmr), in_be32(&lbc->fir), in_be32(&lbc->fcr)); in fsl_elbc_run_command()
214 in_be32(&lbc->fbar), in_be32(&lbc->fpar), in fsl_elbc_run_command()
215 in_be32(&lbc->fbcr), priv->bank); in fsl_elbc_run_command()
218 out_be32(&lbc->lsor, priv->bank); in fsl_elbc_run_command()
225 ltesr = in_be32(&lbc->ltesr); in fsl_elbc_run_command()
231 out_be32(&lbc->ltesr, ctrl->status); in fsl_elbc_run_command()
232 out_be32(&lbc->lteatr, 0); in fsl_elbc_run_command()
236 ctrl->mdr = in_be32(&lbc->mdr); in fsl_elbc_run_command()
241 ctrl->status, ctrl->mdr, in_be32(&lbc->fmr)); in fsl_elbc_run_command()
251 fsl_lbc_t *lbc = ctrl->regs; in fsl_elbc_do_read() local
254 out_be32(&lbc->fir, in fsl_elbc_do_read()
261 out_be32(&lbc->fcr, (NAND_CMD_READ0 << FCR_CMD0_SHIFT) | in fsl_elbc_do_read()
264 out_be32(&lbc->fir, in fsl_elbc_do_read()
271 out_be32(&lbc->fcr, in fsl_elbc_do_read()
274 out_be32(&lbc->fcr, NAND_CMD_READ0 << FCR_CMD0_SHIFT); in fsl_elbc_do_read()
285 fsl_lbc_t *lbc = ctrl->regs; in fsl_elbc_cmdfunc() local
304 out_be32(&lbc->fbcr, 0); /* read entire page to enable ECC */ in fsl_elbc_cmdfunc()
319 out_be32(&lbc->fbcr, mtd->oobsize - column); in fsl_elbc_cmdfunc()
334 out_be32(&lbc->fir, (FIR_OP_CW0 << FIR_OP0_SHIFT) | in fsl_elbc_cmdfunc()
337 out_be32(&lbc->fcr, command << FCR_CMD0_SHIFT); in fsl_elbc_cmdfunc()
342 out_be32(&lbc->fbcr, 256); in fsl_elbc_cmdfunc()
361 out_be32(&lbc->fir, in fsl_elbc_cmdfunc()
366 out_be32(&lbc->fcr, in fsl_elbc_cmdfunc()
370 out_be32(&lbc->fbcr, 0); in fsl_elbc_cmdfunc()
390 out_be32(&lbc->fir, in fsl_elbc_cmdfunc()
400 out_be32(&lbc->fir, in fsl_elbc_cmdfunc()
422 out_be32(&lbc->fcr, fcr); in fsl_elbc_cmdfunc()
438 out_be32(&lbc->fbcr, ctrl->index); in fsl_elbc_cmdfunc()
440 out_be32(&lbc->fbcr, 0); in fsl_elbc_cmdfunc()
450 out_be32(&lbc->fir, in fsl_elbc_cmdfunc()
453 out_be32(&lbc->fcr, NAND_CMD_STATUS << FCR_CMD0_SHIFT); in fsl_elbc_cmdfunc()
454 out_be32(&lbc->fbcr, 1); in fsl_elbc_cmdfunc()
469 out_be32(&lbc->fir, FIR_OP_CM0 << FIR_OP0_SHIFT); in fsl_elbc_cmdfunc()
470 out_be32(&lbc->fcr, NAND_CMD_RESET << FCR_CMD0_SHIFT); in fsl_elbc_cmdfunc()
571 fsl_lbc_t *lbc = ctrl->regs; in fsl_elbc_wait() local
578 out_be32(&lbc->fir, in fsl_elbc_wait()
581 out_be32(&lbc->fcr, NAND_CMD_STATUS << FCR_CMD0_SHIFT); in fsl_elbc_wait()
582 out_be32(&lbc->fbcr, 1); in fsl_elbc_wait()