46 	struct dwmci_host host;  member
72 static uint rockchip_dwmmc_get_mmc_clk(struct dwmci_host *host, uint freq)  in rockchip_dwmmc_get_mmc_clk()  argument
74 	struct udevice *dev = host->priv;  in rockchip_dwmmc_get_mmc_clk()
82 	if (mmc_card_ddr52(host->mmc) && host->mmc->bus_width == 8)  in rockchip_dwmmc_get_mmc_clk()
98 	struct dwmci_host *host = &priv->host;  in rockchip_dwmmc_ofdata_to_platdata()  local
100 	host->name = dev->name;  in rockchip_dwmmc_ofdata_to_platdata()
101 	host->ioaddr = dev_read_addr_ptr(dev);  in rockchip_dwmmc_ofdata_to_platdata()
102 	host->buswidth = dev_read_u32_default(dev, "bus-width", 4);  in rockchip_dwmmc_ofdata_to_platdata()
103 	host->get_mmc_clk = rockchip_dwmmc_get_mmc_clk;  in rockchip_dwmmc_ofdata_to_platdata()
104 	host->priv = dev;  in rockchip_dwmmc_ofdata_to_platdata()
108 		host->dev_index = 0;  in rockchip_dwmmc_ofdata_to_platdata()
110 		host->dev_index = 1;  in rockchip_dwmmc_ofdata_to_platdata()
146 static int rockchip_mmc_get_phase(struct dwmci_host *host, bool sample)  in rockchip_mmc_get_phase()  argument
148 	struct udevice *dev = host->priv;  in rockchip_mmc_get_phase()
160 		raw_value = dwmci_readl(host, SDMMC_TIMING_CON1) >> 1;  in rockchip_mmc_get_phase()
162 		raw_value = dwmci_readl(host, SDMMC_TIMING_CON0) >> 1;  in rockchip_mmc_get_phase()
176 static int rockchip_mmc_set_phase(struct dwmci_host *host, bool sample, int degrees)  in rockchip_mmc_set_phase()  argument
178 	struct udevice *dev = host->priv;  in rockchip_mmc_set_phase()
242 		dwmci_writel(host, SDMMC_TIMING_CON1, HIWORD_UPDATE(raw_value, 0x07ff, 1));  in rockchip_mmc_set_phase()
244 		dwmci_writel(host, SDMMC_TIMING_CON0, HIWORD_UPDATE(raw_value, 0x07ff, 1));  in rockchip_mmc_set_phase()
248 		rockchip_mmc_get_phase(host, sample)  in rockchip_mmc_set_phase()
254 static int rockchip_dwmmc_execute_tuning(struct dwmci_host *host, u32 opcode)  in rockchip_dwmmc_execute_tuning()  argument
256 	struct mmc *mmc = host->mmc;  in rockchip_dwmmc_execute_tuning()
257 	struct udevice *dev = host->priv;  in rockchip_dwmmc_execute_tuning()
283 			rockchip_mmc_set_phase(host, true, TUNING_ITERATION_TO_PHASE(i, num_phases));  in rockchip_dwmmc_execute_tuning()
304 		dev_warn(host->dev, "All phases bad!");  in rockchip_dwmmc_execute_tuning()
362 		rockchip_mmc_set_phase(host, true, real_middle_phase);  in rockchip_dwmmc_execute_tuning()
369 static int rockchip_dwmmc_execute_tuning(struct dwmci_host *host, u32 opcode) { return 0; }  in rockchip_dwmmc_execute_tuning()  argument
370 static int rockchip_mmc_set_phase(struct dwmci_host *host, bool sample, int degrees) { return 0; }  in rockchip_mmc_set_phase()  argument
378 	struct dwmci_host *host = &priv->host;  in rockchip_dwmmc_probe()  local
388 	host->name = dev->name;  in rockchip_dwmmc_probe()
389 	host->ioaddr = map_sysmem(dtplat->reg[0], dtplat->reg[1]);  in rockchip_dwmmc_probe()
390 	host->buswidth = dtplat->bus_width;  in rockchip_dwmmc_probe()
391 	host->get_mmc_clk = rockchip_dwmmc_get_mmc_clk;  in rockchip_dwmmc_probe()
392 	host->execute_tuning = rockchip_dwmmc_execute_tuning;  in rockchip_dwmmc_probe()
393 	host->priv = dev;  in rockchip_dwmmc_probe()
394 	host->dev_index = 0;  in rockchip_dwmmc_probe()
408 	priv->usrid = dwmci_readl(host, DWMCI_USRID);  in rockchip_dwmmc_probe()
416 	host->execute_tuning = rockchip_dwmmc_execute_tuning;  in rockchip_dwmmc_probe()
418 	host->fifoth_val = MSIZE(DWMCI_MSIZE) |  in rockchip_dwmmc_probe()
422 	host->fifo_mode = priv->fifo_mode;  in rockchip_dwmmc_probe()
425 	host->stride_pio = true;  in rockchip_dwmmc_probe()
427 	host->stride_pio = false;  in rockchip_dwmmc_probe()
440 	dwmci_setup_cfg(&plat->cfg, host, priv->minmax[1], priv->minmax[0]);  in rockchip_dwmmc_probe()
449 			ret = rockchip_mmc_set_phase(host, true, plat->mmc.default_phase);  in rockchip_dwmmc_probe()
457 	host->mmc = &plat->mmc;  in rockchip_dwmmc_probe()
458 	host->mmc->priv = &priv->host;  in rockchip_dwmmc_probe()
459 	host->mmc->dev = dev;  in rockchip_dwmmc_probe()
460 	upriv->mmc = host->mmc;  in rockchip_dwmmc_probe()