31 	struct davinci_mmc_regs *regs = host->reg_base;  in dmmc_set_clock()  local
39 	set_val(&regs->mmcclk, 0);  in dmmc_set_clock()
54 	set_val(&regs->mmcclk, (clkrt | MMCCLK_CLKEN));  in dmmc_set_clock()
59 dmmc_wait_fifo_status(volatile struct davinci_mmc_regs *regs, uint status)  in dmmc_wait_fifo_status()  argument
63 	while (--wdog && ((get_val(&regs->mmcst1) & status) != status))  in dmmc_wait_fifo_status()
66 	if (!(get_val(&regs->mmcctl) & MMCCTL_WIDTH_4_BIT))  in dmmc_wait_fifo_status()
76 static int dmmc_busy_wait(volatile struct davinci_mmc_regs *regs)  in dmmc_busy_wait()  argument
80 	while (--wdog && (get_val(&regs->mmcst1) & MMCST1_BUSY))  in dmmc_busy_wait()
90 static int dmmc_check_status(volatile struct davinci_mmc_regs *regs,  in dmmc_check_status()  argument
99 			mmcstatus = get_val(&regs->mmcst1);  in dmmc_check_status()
115 		mmcstatus = get_val(&regs->mmcst0);  in dmmc_check_status()
119 			get_val(&regs->mmcst1));  in dmmc_check_status()
131 	volatile struct davinci_mmc_regs *regs = host->reg_base;  in dmmc_send_cmd()  local
138 	mmcstatus = get_val(&regs->mmcst0);  in dmmc_send_cmd()
143 	dmmc_busy_wait(regs);  in dmmc_send_cmd()
167 	set_val(&regs->mmcim, 0);  in dmmc_send_cmd()
174 		set_val(&regs->mmcfifoctl,  in dmmc_send_cmd()
182 			set_val(&regs->mmcfifoctl, MMCFIFOCTL_FIFOLEV);  in dmmc_send_cmd()
184 			set_val(&regs->mmcfifoctl,  in dmmc_send_cmd()
190 		set_val(&regs->mmctod, 0xFFFF);  in dmmc_send_cmd()
191 		set_val(&regs->mmcnblk, (data->blocks & MMCNBLK_NBLK_MASK));  in dmmc_send_cmd()
192 		set_val(&regs->mmcblen, (data->blocksize & MMCBLEN_BLEN_MASK));  in dmmc_send_cmd()
200 				set_val(&regs->mmcdxr, val);  in dmmc_send_cmd()
206 		set_val(&regs->mmcblen, 0);  in dmmc_send_cmd()
207 		set_val(&regs->mmcnblk, 0);  in dmmc_send_cmd()
210 	set_val(&regs->mmctor, 0x1FFF);  in dmmc_send_cmd()
213 	set_val(&regs->mmcarghl, cmd->cmdarg);  in dmmc_send_cmd()
214 	set_val(&regs->mmccmd, cmddata);  in dmmc_send_cmd()
222 	mmcstatus = get_val(&regs->mmcst0);  in dmmc_send_cmd()
223 	err = dmmc_check_status(regs, &mmcstatus, status_rdy, status_err);  in dmmc_send_cmd()
229 		dmmc_busy_wait(regs);  in dmmc_send_cmd()
235 			cmd->response[0] = get_val(&regs->mmcrsp67);  in dmmc_send_cmd()
236 			cmd->response[1] = get_val(&regs->mmcrsp45);  in dmmc_send_cmd()
237 			cmd->response[2] = get_val(&regs->mmcrsp23);  in dmmc_send_cmd()
238 			cmd->response[3] = get_val(&regs->mmcrsp01);  in dmmc_send_cmd()
240 			cmd->response[0] = get_val(&regs->mmcrsp67);  in dmmc_send_cmd()
262 		err = dmmc_check_status(regs, &mmcstatus, status_rdy,  in dmmc_send_cmd()
276 				dmmc_wait_fifo_status(regs, 0x4a);  in dmmc_send_cmd()
278 				dmmc_wait_fifo_status(regs, 0x40);  in dmmc_send_cmd()
284 				cmddata = get_val(&regs->mmcdrr);  in dmmc_send_cmd()
297 			dmmc_wait_fifo_status(regs, MMCST1_FIFOEMP);  in dmmc_send_cmd()
300 				set_val(&regs->mmcdxr, cmddata);  in dmmc_send_cmd()
304 			dmmc_busy_wait(regs);  in dmmc_send_cmd()
308 	err = dmmc_check_status(regs, &mmcstatus, MMCST0_DATDNE, status_err);  in dmmc_send_cmd()
319 	struct davinci_mmc_regs *regs = host->reg_base;  in dmmc_init()  local
325 	get_val(&regs->mmcst0);  in dmmc_init()
326 	get_val(&regs->mmcst1);  in dmmc_init()
329 	set_bit(&regs->mmcctl, MMCCTL_DATRST);  in dmmc_init()
330 	set_bit(&regs->mmcctl, MMCCTL_CMDRST);  in dmmc_init()
333 	set_val(&regs->mmcclk, 0x0);  in dmmc_init()
334 	set_val(&regs->mmctor, 0x1FFF);  in dmmc_init()
335 	set_val(&regs->mmctod, 0xFFFF);  in dmmc_init()
338 	clear_bit(&regs->mmcctl, MMCCTL_DATRST);  in dmmc_init()
339 	clear_bit(&regs->mmcctl, MMCCTL_CMDRST);  in dmmc_init()
344 	set_val(&regs->mmcfifoctl, (MMCFIFOCTL_FIFOLEV | MMCFIFOCTL_FIFORST));  in dmmc_init()
345 	set_val(&regs->mmcfifoctl, MMCFIFOCTL_FIFOLEV);  in dmmc_init()
354 	struct davinci_mmc_regs *regs = host->reg_base;  in dmmc_set_ios()  local
358 		set_bit(&regs->mmcctl, MMCCTL_WIDTH_4_BIT);  in dmmc_set_ios()
360 		clear_bit(&regs->mmcctl, MMCCTL_WIDTH_4_BIT);  in dmmc_set_ios()