56 static struct dma_reg *dma = (struct dma_reg *)DMA_BASE;  variable
72 		writel(0, &dma->config);  in lpc32xx_dma_get_channel()
73 		writel(0, &dma->sync);  in lpc32xx_dma_get_channel()
76 		writel(0xFF, &dma->int_tc_clear);  in lpc32xx_dma_get_channel()
77 		writel(0xFF, &dma->raw_tc_stat);  in lpc32xx_dma_get_channel()
78 		writel(0xFF, &dma->int_err_clear);  in lpc32xx_dma_get_channel()
79 		writel(0xFF, &dma->raw_err_stat);  in lpc32xx_dma_get_channel()
82 		writel(DMAC_CTRL_ENABLE, &dma->config);  in lpc32xx_dma_get_channel()
102 	writel(BIT_MASK(channel), &dma->int_tc_clear);  in lpc32xx_dma_start_xfer()
103 	writel(BIT_MASK(channel), &dma->int_err_clear);  in lpc32xx_dma_start_xfer()
104 	writel(desc->dma_src, &dma->dma_chan[channel].src_addr);  in lpc32xx_dma_start_xfer()
105 	writel(desc->dma_dest, &dma->dma_chan[channel].dest_addr);  in lpc32xx_dma_start_xfer()
106 	writel(desc->next_lli, &dma->dma_chan[channel].lli);  in lpc32xx_dma_start_xfer()
107 	writel(desc->next_ctrl, &dma->dma_chan[channel].control);  in lpc32xx_dma_start_xfer()
108 	writel(config, &dma->dma_chan[channel].config_ch);  in lpc32xx_dma_start_xfer()
126 		reg = readl(&dma->raw_tc_stat);  in lpc32xx_dma_wait_status()
127 		reg |= readl(dma->raw_err_stat);  in lpc32xx_dma_wait_status()
138 	if (unlikely(readl(&dma->raw_err_stat) & BIT_MASK(channel))) {  in lpc32xx_dma_wait_status()
139 		setbits_le32(&dma->int_err_clear, BIT_MASK(channel));  in lpc32xx_dma_wait_status()
140 		setbits_le32(&dma->raw_err_stat, BIT_MASK(channel));  in lpc32xx_dma_wait_status()
144 	setbits_le32(&dma->int_tc_clear, BIT_MASK(channel));  in lpc32xx_dma_wait_status()
145 	setbits_le32(&dma->raw_tc_stat, BIT_MASK(channel));  in lpc32xx_dma_wait_status()