122 					dram_info->wl_val[cs][pup][P] = phase;  in ddr3_write_leveling_hw()
123 					dram_info->wl_val[cs][pup][D] = delay;  in ddr3_write_leveling_hw()
124 					dram_info->wl_val[cs][pup][S] =  in ddr3_write_leveling_hw()
129 					dram_info->wl_val[cs][pup][DQS] =  in ddr3_write_leveling_hw()
148 						   dram_info->wl_val[cs][pup]  in ddr3_write_leveling_hw()
152 						   dram_info->wl_val[cs][pup]  in ddr3_write_leveling_hw()
339 							dram_info->wl_val[cs]  in ddr3_wl_supplement()
345 							    ((dram_info->wl_val  in ddr3_wl_supplement()
350 							dram_info->wl_val[cs]  in ddr3_wl_supplement()
354 							    dram_info->wl_val  in ddr3_wl_supplement()
366 							    dram_info->wl_val  in ddr3_wl_supplement()
370 							    dram_info->wl_val  in ddr3_wl_supplement()
383 							dram_info->wl_val[cs]  in ddr3_wl_supplement()
386 							dram_info->wl_val[cs]  in ddr3_wl_supplement()
410 				sum += dram_info->wl_val[cs][pup][S];  in ddr3_wl_supplement()
413 				sum += dram_info->wl_val[cs][ECC_PUP][S];  in ddr3_wl_supplement()
545 					dram_info->wl_val[cs][pup][P] = phase;  in ddr3_write_leveling_hw_reg_dimm()
546 					dram_info->wl_val[cs][pup][D] = delay;  in ddr3_write_leveling_hw_reg_dimm()
555 						dram_info->wl_val[cs][pup][P] =  in ddr3_write_leveling_hw_reg_dimm()
557 						dram_info->wl_val[cs][pup][D] =  in ddr3_write_leveling_hw_reg_dimm()
560 					dram_info->wl_val[cs][pup][S] =  in ddr3_write_leveling_hw_reg_dimm()
565 					dram_info->wl_val[cs][pup][DQS] =  in ddr3_write_leveling_hw_reg_dimm()
584 						   dram_info->wl_val[cs][pup]  in ddr3_write_leveling_hw_reg_dimm()
588 						   dram_info->wl_val[cs][pup]  in ddr3_write_leveling_hw_reg_dimm()
719 	memset(dram_info->wl_val, 0, sizeof(u32) * MAX_CS * MAX_PUP_NUM * 7);  in ddr3_write_leveling_sw()
1267 				if (dram_info->wl_val[cs][pup][S] == 0) {  in ddr3_write_leveling_single_cs()
1269 					dram_info->wl_val[cs][pup][P] = phase;  in ddr3_write_leveling_single_cs()
1271 					dram_info->wl_val[cs][pup][D] = delay;  in ddr3_write_leveling_single_cs()
1279 				    && (dram_info->wl_val[cs][pup][S] == 0)) {  in ddr3_write_leveling_single_cs()
1285 					dram_info->wl_val[cs][pup][S] = 1;  in ddr3_write_leveling_single_cs()
1306 		DEBUG_WL_D((u32) dram_info->wl_val[cs][pup][P], 1);  in ddr3_write_leveling_single_cs()
1308 		DEBUG_WL_D((u32) dram_info->wl_val[cs][pup][D], 2);  in ddr3_write_leveling_single_cs()
1322 		phase = dram_info->wl_val[cs][pup][P];  in ddr3_write_leveling_single_cs()
1323 		delay = dram_info->wl_val[cs][pup][D];  in ddr3_write_leveling_single_cs()