Lines Matching refs:pup
50 static void ddr3_write_ctrl_pup_reg(int bc_acc, u32 pup, u32 reg_addr,
67 u32 reg, phase, delay, cs, pup; in ddr3_write_leveling_hw() local
109 for (pup = 0; in ddr3_write_leveling_hw()
110 pup < dram_info->num_of_total_pups; in ddr3_write_leveling_hw()
111 pup++) { in ddr3_write_leveling_hw()
112 if (pup == dram_info->num_of_std_pups in ddr3_write_leveling_hw()
114 pup = ECC_PUP; in ddr3_write_leveling_hw()
117 pup); in ddr3_write_leveling_hw()
122 dram_info->wl_val[cs][pup][P] = phase; in ddr3_write_leveling_hw()
123 dram_info->wl_val[cs][pup][D] = delay; in ddr3_write_leveling_hw()
124 dram_info->wl_val[cs][pup][S] = in ddr3_write_leveling_hw()
128 cs, pup); in ddr3_write_leveling_hw()
129 dram_info->wl_val[cs][pup][DQS] = in ddr3_write_leveling_hw()
138 for (pup = 0; in ddr3_write_leveling_hw()
139 pup < dram_info->num_of_total_pups; in ddr3_write_leveling_hw()
140 pup++) { in ddr3_write_leveling_hw()
141 if (pup == dram_info->num_of_std_pups in ddr3_write_leveling_hw()
143 pup = ECC_PUP; in ddr3_write_leveling_hw()
145 DEBUG_WL_D((u32) pup, 1); in ddr3_write_leveling_hw()
148 dram_info->wl_val[cs][pup] in ddr3_write_leveling_hw()
152 dram_info->wl_val[cs][pup] in ddr3_write_leveling_hw()
187 u32 cs, cnt, pup_num, sum, phase, delay, max_pup_num, pup, sdram_offset; in ddr3_wl_supplement() local
293 for (pup = 0; pup < max_pup_num; pup++) { in ddr3_wl_supplement()
295 pup_num = (ecc) ? ECC_PUP : pup; in ddr3_wl_supplement()
296 if (pup < 4) { /* lower 32 bit */ in ddr3_wl_supplement()
297 tmp_pup = pup; in ddr3_wl_supplement()
301 tmp_pup = pup - 4; in ddr3_wl_supplement()
318 + pup), 2); in ddr3_wl_supplement()
325 pup) - sdram_pup_val; in ddr3_wl_supplement()
333 pup); in ddr3_wl_supplement()
360 pup * (1 - ecc) + in ddr3_wl_supplement()
391 pup * (1 - ecc) + in ddr3_wl_supplement()
396 pup = (ecc) ? max_pup_num : pup; in ddr3_wl_supplement()
409 for (pup = 0; pup < dram_info->num_of_std_pups; pup++) in ddr3_wl_supplement()
410 sum += dram_info->wl_val[cs][pup][S]; in ddr3_wl_supplement()
433 for (pup = 0; pup < dram_info->num_of_total_pups; pup++) { in ddr3_wl_supplement()
434 if (pup == dram_info->num_of_std_pups in ddr3_wl_supplement()
436 pup = ECC_PUP; in ddr3_wl_supplement()
437 reg = ddr3_read_pup_reg(PUP_WL_MODE, cs, pup); in ddr3_wl_supplement()
475 u32 reg, phase, delay, cs, pup, pup_num; in ddr3_write_leveling_hw_reg_dimm() local
489 for (pup = 0; pup <= dram_info->num_of_total_pups; pup++) { in ddr3_write_leveling_hw_reg_dimm()
492 ddr3_write_ctrl_pup_reg(1, pup, CNTRL_PUP_DESKEW + pup, in ddr3_write_leveling_hw_reg_dimm()
532 for (pup = 0; in ddr3_write_leveling_hw_reg_dimm()
533 pup < dram_info->num_of_total_pups; in ddr3_write_leveling_hw_reg_dimm()
534 pup++) { in ddr3_write_leveling_hw_reg_dimm()
535 if (pup == dram_info->num_of_std_pups in ddr3_write_leveling_hw_reg_dimm()
537 pup = ECC_BIT; in ddr3_write_leveling_hw_reg_dimm()
540 pup); in ddr3_write_leveling_hw_reg_dimm()
545 dram_info->wl_val[cs][pup][P] = phase; in ddr3_write_leveling_hw_reg_dimm()
546 dram_info->wl_val[cs][pup][D] = delay; in ddr3_write_leveling_hw_reg_dimm()
553 cs, pup, 0, in ddr3_write_leveling_hw_reg_dimm()
555 dram_info->wl_val[cs][pup][P] = in ddr3_write_leveling_hw_reg_dimm()
557 dram_info->wl_val[cs][pup][D] = in ddr3_write_leveling_hw_reg_dimm()
560 dram_info->wl_val[cs][pup][S] = in ddr3_write_leveling_hw_reg_dimm()
564 cs, pup); in ddr3_write_leveling_hw_reg_dimm()
565 dram_info->wl_val[cs][pup][DQS] = in ddr3_write_leveling_hw_reg_dimm()
576 for (pup = 0; in ddr3_write_leveling_hw_reg_dimm()
577 pup < dram_info->num_of_total_pups; in ddr3_write_leveling_hw_reg_dimm()
578 pup++) { in ddr3_write_leveling_hw_reg_dimm()
581 DEBUG_WL_D((u32) pup, 1); in ddr3_write_leveling_hw_reg_dimm()
584 dram_info->wl_val[cs][pup] in ddr3_write_leveling_hw_reg_dimm()
588 dram_info->wl_val[cs][pup] in ddr3_write_leveling_hw_reg_dimm()
609 for (pup = 0; pup <= dram_info->num_of_total_pups; in ddr3_write_leveling_hw_reg_dimm()
610 pup++) { in ddr3_write_leveling_hw_reg_dimm()
611 ddr3_write_ctrl_pup_reg(1, pup, in ddr3_write_leveling_hw_reg_dimm()
612 CNTRL_PUP_DESKEW + pup, 0); in ddr3_write_leveling_hw_reg_dimm()
621 for (pup = 0; in ddr3_write_leveling_hw_reg_dimm()
622 pup < dram_info->num_of_total_pups; in ddr3_write_leveling_hw_reg_dimm()
623 pup++) { in ddr3_write_leveling_hw_reg_dimm()
625 pup_num = (pup == dram_info->num_of_std_pups) ? in ddr3_write_leveling_hw_reg_dimm()
626 ECC_BIT : pup; in ddr3_write_leveling_hw_reg_dimm()
638 for (pup = 0; pup <= dram_info->num_of_total_pups; in ddr3_write_leveling_hw_reg_dimm()
639 pup++) { in ddr3_write_leveling_hw_reg_dimm()
640 ddr3_write_ctrl_pup_reg(1, pup, in ddr3_write_leveling_hw_reg_dimm()
641 CNTRL_PUP_DESKEW + pup, 0); in ddr3_write_leveling_hw_reg_dimm()
660 u32 reg, cs, cnt, pup, max_pup_num; in ddr3_write_leveling_sw() local
774 for (pup = 0; pup < max_pup_num; pup++) { in ddr3_write_leveling_sw()
775 if (((res[cs] >> pup) & 0x1) == 0) { in ddr3_write_leveling_sw()
777 pup, 1); in ddr3_write_leveling_sw()
885 u32 reg, cs, cnt, pup; in ddr3_write_leveling_sw_reg_dimm() local
905 for (pup = 0; pup <= dram_info->num_of_total_pups; pup++) { in ddr3_write_leveling_sw_reg_dimm()
908 ddr3_write_ctrl_pup_reg(1, pup, CNTRL_PUP_DESKEW + pup, in ddr3_write_leveling_sw_reg_dimm()
1104 for (pup = 0; pup <= dram_info->num_of_total_pups; pup++) { in ddr3_write_leveling_sw_reg_dimm()
1105 ddr3_write_ctrl_pup_reg(1, pup, CNTRL_PUP_DESKEW + pup, in ddr3_write_leveling_sw_reg_dimm()
1128 u32 reg, pup_num, delay, phase, phaseMax, max_pup_num, pup, in ddr3_write_leveling_single_cs() local
1263 for (pup = 0; pup < (max_pup_num); pup++) { in ddr3_write_leveling_single_cs()
1265 pup_num = (pup == dram_info->num_of_std_pups) ? in ddr3_write_leveling_single_cs()
1266 ECC_BIT : pup; in ddr3_write_leveling_single_cs()
1267 if (dram_info->wl_val[cs][pup][S] == 0) { in ddr3_write_leveling_single_cs()
1269 dram_info->wl_val[cs][pup][P] = phase; in ddr3_write_leveling_single_cs()
1271 dram_info->wl_val[cs][pup][D] = delay; in ddr3_write_leveling_single_cs()
1279 && (dram_info->wl_val[cs][pup][S] == 0)) { in ddr3_write_leveling_single_cs()
1285 dram_info->wl_val[cs][pup][S] = 1; in ddr3_write_leveling_single_cs()
1302 for (pup = 0; pup < (max_pup_num); pup++) { in ddr3_write_leveling_single_cs()
1304 DEBUG_WL_D((u32) pup, 1); in ddr3_write_leveling_single_cs()
1306 DEBUG_WL_D((u32) dram_info->wl_val[cs][pup][P], 1); in ddr3_write_leveling_single_cs()
1308 DEBUG_WL_D((u32) dram_info->wl_val[cs][pup][D], 2); in ddr3_write_leveling_single_cs()
1319 for (pup = 0; pup < (max_pup_num); pup++) { in ddr3_write_leveling_single_cs()
1321 pup_num = (pup == dram_info->num_of_std_pups) ? ECC_BIT : pup; in ddr3_write_leveling_single_cs()
1322 phase = dram_info->wl_val[cs][pup][P]; in ddr3_write_leveling_single_cs()
1323 delay = dram_info->wl_val[cs][pup][D]; in ddr3_write_leveling_single_cs()
1339 static void ddr3_write_ctrl_pup_reg(int bc_acc, u32 pup, u32 reg_addr, u32 data) in ddr3_write_ctrl_pup_reg() argument
1353 reg |= (pup << REG_PHY_PUP_OFFS); in ddr3_write_ctrl_pup_reg()