49 					 MV_DRAM_INFO *dram_info);
65 int ddr3_write_leveling_hw(u32 freq, MV_DRAM_INFO *dram_info)  in ddr3_write_leveling_hw()  argument
87 	reg |= (dram_info->cs_ena << (REG_DRAM_TRAINING_CS_OFFS));  in ddr3_write_leveling_hw()
108 			if (dram_info->cs_ena & (1 << cs)) {  in ddr3_write_leveling_hw()
110 				     pup < dram_info->num_of_total_pups;  in ddr3_write_leveling_hw()
112 					if (pup == dram_info->num_of_std_pups  in ddr3_write_leveling_hw()
113 					    && dram_info->ecc_ena)  in ddr3_write_leveling_hw()
122 					dram_info->wl_val[cs][pup][P] = phase;  in ddr3_write_leveling_hw()
123 					dram_info->wl_val[cs][pup][D] = delay;  in ddr3_write_leveling_hw()
124 					dram_info->wl_val[cs][pup][S] =  in ddr3_write_leveling_hw()
129 					dram_info->wl_val[cs][pup][DQS] =  in ddr3_write_leveling_hw()
139 				     pup < dram_info->num_of_total_pups;  in ddr3_write_leveling_hw()
141 					if (pup == dram_info->num_of_std_pups  in ddr3_write_leveling_hw()
142 					    && dram_info->ecc_ena)  in ddr3_write_leveling_hw()
148 						   dram_info->wl_val[cs][pup]  in ddr3_write_leveling_hw()
152 						   dram_info->wl_val[cs][pup]  in ddr3_write_leveling_hw()
185 int ddr3_wl_supplement(MV_DRAM_INFO *dram_info)  in ddr3_wl_supplement()  argument
194 	ddr_width = dram_info->ddr_width;  in ddr3_wl_supplement()
230 		if (dram_info->cs_ena & (1 << cs)) {  in ddr3_wl_supplement()
238 				for (ecc = 0; ecc < (dram_info->ecc_ena + 1);  in ddr3_wl_supplement()
247 					    dram_info->num_of_std_pups * (1 -  in ddr3_wl_supplement()
256 					    (dram_info->ecc_ena *  in ddr3_wl_supplement()
339 							dram_info->wl_val[cs]  in ddr3_wl_supplement()
345 							    ((dram_info->wl_val  in ddr3_wl_supplement()
350 							dram_info->wl_val[cs]  in ddr3_wl_supplement()
354 							    dram_info->wl_val  in ddr3_wl_supplement()
366 							    dram_info->wl_val  in ddr3_wl_supplement()
370 							    dram_info->wl_val  in ddr3_wl_supplement()
383 							dram_info->wl_val[cs]  in ddr3_wl_supplement()
386 							dram_info->wl_val[cs]  in ddr3_wl_supplement()
409 			for (pup = 0; pup < dram_info->num_of_std_pups; pup++)  in ddr3_wl_supplement()
410 				sum += dram_info->wl_val[cs][pup][S];  in ddr3_wl_supplement()
412 			if (dram_info->ecc_ena)  in ddr3_wl_supplement()
413 				sum += dram_info->wl_val[cs][ECC_PUP][S];  in ddr3_wl_supplement()
416 			if (sum < (WL_HI_FREQ_STATE * (dram_info->num_of_total_pups))) {  in ddr3_wl_supplement()
425 	dram_info->wl_max_phase = 0;  in ddr3_wl_supplement()
426 	dram_info->wl_min_phase = 10;  in ddr3_wl_supplement()
432 		if (dram_info->cs_ena & (1 << cs)) {  in ddr3_wl_supplement()
433 			for (pup = 0; pup < dram_info->num_of_total_pups; pup++) {  in ddr3_wl_supplement()
434 				if (pup == dram_info->num_of_std_pups  in ddr3_wl_supplement()
435 				    && dram_info->ecc_ena)  in ddr3_wl_supplement()
441 				if (phase > dram_info->wl_max_phase)  in ddr3_wl_supplement()
442 					dram_info->wl_max_phase = phase;  in ddr3_wl_supplement()
443 				if (phase < dram_info->wl_min_phase)  in ddr3_wl_supplement()
444 					dram_info->wl_min_phase = phase;  in ddr3_wl_supplement()
473 int ddr3_write_leveling_hw_reg_dimm(u32 freq, MV_DRAM_INFO *dram_info)  in ddr3_write_leveling_hw_reg_dimm()  argument
481 	if (dram_info->num_cs > 2) {  in ddr3_write_leveling_hw_reg_dimm()
489 		for (pup = 0; pup <= dram_info->num_of_total_pups; pup++) {  in ddr3_write_leveling_hw_reg_dimm()
510 	reg |= (dram_info->cs_ena << (REG_DRAM_TRAINING_CS_OFFS));  in ddr3_write_leveling_hw_reg_dimm()
531 			if (dram_info->cs_ena & (1 << cs)) {  in ddr3_write_leveling_hw_reg_dimm()
533 				     pup < dram_info->num_of_total_pups;  in ddr3_write_leveling_hw_reg_dimm()
535 					if (pup == dram_info->num_of_std_pups  in ddr3_write_leveling_hw_reg_dimm()
536 					    && dram_info->ecc_ena)  in ddr3_write_leveling_hw_reg_dimm()
545 					dram_info->wl_val[cs][pup][P] = phase;  in ddr3_write_leveling_hw_reg_dimm()
546 					dram_info->wl_val[cs][pup][D] = delay;  in ddr3_write_leveling_hw_reg_dimm()
555 						dram_info->wl_val[cs][pup][P] =  in ddr3_write_leveling_hw_reg_dimm()
557 						dram_info->wl_val[cs][pup][D] =  in ddr3_write_leveling_hw_reg_dimm()
560 					dram_info->wl_val[cs][pup][S] =  in ddr3_write_leveling_hw_reg_dimm()
565 					dram_info->wl_val[cs][pup][DQS] =  in ddr3_write_leveling_hw_reg_dimm()
577 				     pup < dram_info->num_of_total_pups;  in ddr3_write_leveling_hw_reg_dimm()
584 						   dram_info->wl_val[cs][pup]  in ddr3_write_leveling_hw_reg_dimm()
588 						   dram_info->wl_val[cs][pup]  in ddr3_write_leveling_hw_reg_dimm()
609 			for (pup = 0; pup <= dram_info->num_of_total_pups;  in ddr3_write_leveling_hw_reg_dimm()
620 			if (dram_info->cs_ena & (1 << cs)) {  in ddr3_write_leveling_hw_reg_dimm()
622 				     pup < dram_info->num_of_total_pups;  in ddr3_write_leveling_hw_reg_dimm()
625 					pup_num = (pup == dram_info->num_of_std_pups) ?  in ddr3_write_leveling_hw_reg_dimm()
638 			for (pup = 0; pup <= dram_info->num_of_total_pups;  in ddr3_write_leveling_hw_reg_dimm()
658 int ddr3_write_leveling_sw(u32 freq, int ratio_2to1, MV_DRAM_INFO *dram_info)  in ddr3_write_leveling_sw()  argument
662 	max_pup_num = dram_info->num_of_total_pups;  in ddr3_write_leveling_sw()
680 		if (dram_info->cs_ena & (1 << cs)) {  in ddr3_write_leveling_sw()
683 			reg |= odt_static[dram_info->cs_ena][cs];  in ddr3_write_leveling_sw()
719 	memset(dram_info->wl_val, 0, sizeof(u32) * MAX_CS * MAX_PUP_NUM * 7);  in ddr3_write_leveling_sw()
723 		if (dram_info->cs_ena & (1 << cs)) {  in ddr3_write_leveling_sw()
750 			reg |= odt_static[dram_info->cs_ena][cs];  in ddr3_write_leveling_sw()
771 							  dram_info)) {  in ddr3_write_leveling_sw()
838 		if (dram_info->cs_ena & (1 << cs)) {  in ddr3_write_leveling_sw()
842 			reg |= odt_static[dram_info->cs_ena][cs];  in ddr3_write_leveling_sw()
883 				    MV_DRAM_INFO *dram_info)  in ddr3_write_leveling_sw_reg_dimm()  argument
905 		for (pup = 0; pup <= dram_info->num_of_total_pups; pup++) {  in ddr3_write_leveling_sw_reg_dimm()
915 		if (dram_info->cs_ena & (1 << cs)) {  in ddr3_write_leveling_sw_reg_dimm()
918 			reg |= odt_static[dram_info->cs_ena][cs];  in ddr3_write_leveling_sw_reg_dimm()
956 		if (dram_info->cs_ena & (1 << cs)) {  in ddr3_write_leveling_sw_reg_dimm()
987 			reg |= odt_static[dram_info->cs_ena][cs];  in ddr3_write_leveling_sw_reg_dimm()
1012 							  dram_info)) {  in ddr3_write_leveling_sw_reg_dimm()
1070 		if (dram_info->cs_ena & (1 << cs)) {  in ddr3_write_leveling_sw_reg_dimm()
1074 			reg |= odt_static[dram_info->cs_ena][cs];  in ddr3_write_leveling_sw_reg_dimm()
1104 		for (pup = 0; pup <= dram_info->num_of_total_pups; pup++) {  in ddr3_write_leveling_sw_reg_dimm()
1126 					 u32 *result, MV_DRAM_INFO *dram_info)  in ddr3_write_leveling_single_cs()  argument
1131 	max_pup_num = dram_info->num_of_total_pups;  in ddr3_write_leveling_single_cs()
1265 				pup_num = (pup == dram_info->num_of_std_pups) ?  in ddr3_write_leveling_single_cs()
1267 				if (dram_info->wl_val[cs][pup][S] == 0) {  in ddr3_write_leveling_single_cs()
1269 					dram_info->wl_val[cs][pup][P] = phase;  in ddr3_write_leveling_single_cs()
1271 					dram_info->wl_val[cs][pup][D] = delay;  in ddr3_write_leveling_single_cs()
1279 				    && (dram_info->wl_val[cs][pup][S] == 0)) {  in ddr3_write_leveling_single_cs()
1285 					dram_info->wl_val[cs][pup][S] = 1;  in ddr3_write_leveling_single_cs()
1306 		DEBUG_WL_D((u32) dram_info->wl_val[cs][pup][P], 1);  in ddr3_write_leveling_single_cs()
1308 		DEBUG_WL_D((u32) dram_info->wl_val[cs][pup][D], 2);  in ddr3_write_leveling_single_cs()
1321 		pup_num = (pup == dram_info->num_of_std_pups) ? ECC_BIT : pup;  in ddr3_write_leveling_single_cs()
1322 		phase = dram_info->wl_val[cs][pup][P];  in ddr3_write_leveling_single_cs()
1323 		delay = dram_info->wl_val[cs][pup][D];  in ddr3_write_leveling_single_cs()