67 	u32 reg, phase, delay, cs, pup;  in ddr3_write_leveling_hw()  local
121 					delay = reg & PUP_DELAY_MASK;  in ddr3_write_leveling_hw()
123 					dram_info->wl_val[cs][pup][D] = delay;  in ddr3_write_leveling_hw()
187 	u32 cs, cnt, pup_num, sum, phase, delay, max_pup_num, pup, sdram_offset;  in ddr3_wl_supplement()  local
353 							delay =  in ddr3_wl_supplement()
362 							     phase, delay);  in ddr3_wl_supplement()
369 							delay =  in ddr3_wl_supplement()
376 								&& (delay <=  in ddr3_wl_supplement()
382 							delay = 0x0;  in ddr3_wl_supplement()
388 							    [D] = delay;  in ddr3_wl_supplement()
393 							     phase, delay);  in ddr3_wl_supplement()
475 	u32 reg, phase, delay, cs, pup, pup_num;  in ddr3_write_leveling_hw_reg_dimm()  local
544 					delay = reg & PUP_DELAY_MASK;  in ddr3_write_leveling_hw_reg_dimm()
546 					dram_info->wl_val[cs][pup][D] = delay;  in ddr3_write_leveling_hw_reg_dimm()
547 					if ((phase == 1) && (delay >= 0x1D)) {  in ddr3_write_leveling_hw_reg_dimm()
1128 	u32 reg, pup_num, delay, phase, phaseMax, max_pup_num, pup,  in ddr3_write_leveling_single_cs()  local
1223 		for (delay = 0; delay < MAX_DELAY; delay++) {  in ddr3_write_leveling_single_cs()
1226 					   delay);  in ddr3_write_leveling_single_cs()
1233 			DEBUG_WL_FULL_D((u32) delay, 1);  in ddr3_write_leveling_single_cs()
1271 					dram_info->wl_val[cs][pup][D] = delay;  in ddr3_write_leveling_single_cs()
1294 				delay = MAX_DELAY;  in ddr3_write_leveling_single_cs()
1323 		delay = dram_info->wl_val[cs][pup][D];  in ddr3_write_leveling_single_cs()
1324 		ddr3_write_pup_reg(PUP_WL_MODE, cs, pup_num, phase, delay);  in ddr3_write_leveling_single_cs()