marvell/axp/ddr3_spd.c

185 static u32 ddr3_get_max_val(u32 spd_val, u32 dimm_num, u32 static_val);
186 static u32 ddr3_get_min_val(u32 spd_val, u32 dimm_num, u32 static_val);
581 	u32 stat_val, spd_val;  local
790 	spd_val = ddr3_div(sum_info.min_active_to_precharge,
794 	tmp = ddr3_get_max_val(spd_val, dimm_num, stat_val);
800 	spd_val = ddr3_div(sum_info.min_ras_to_cas_delay, ddr_clk_time, 1);
803 	tmp = ddr3_get_max_val(spd_val, dimm_num, stat_val);
808 	spd_val = ddr3_div(sum_info.min_row_precharge_time, ddr_clk_time, 1);
811 	tmp = ddr3_get_max_val(spd_val, dimm_num, stat_val);
816 	spd_val = ddr3_div(sum_info.min_write_recovery_time, ddr_clk_time, 1);
819 	tmp = ddr3_get_max_val(spd_val, dimm_num, stat_val);
824 	spd_val = ddr3_div(sum_info.min_write_to_read_cmd_delay, ddr_clk_time, 1);
827 	tmp = ddr3_get_max_val(spd_val, dimm_num, stat_val);
832 	spd_val = ddr3_div(sum_info.min_row_active_to_row_active, ddr_clk_time, 1);
835 	tmp = ddr3_get_max_val(spd_val, dimm_num, stat_val);
840 	spd_val = ddr3_div(sum_info.min_read_to_prech_cmd_delay, ddr_clk_time, 1);
843 	tmp = ddr3_get_max_val(spd_val, dimm_num, stat_val);
857 	spd_val = ddr3_div(sum_info.min_refresh_recovery, ddr_clk_time, 1);
860 	tmp = ddr3_get_max_val(spd_val, dimm_num, stat_val);
872 	spd_val = ddr3_div(tmp, ddr_clk_time, 0);
875 	tmp = ddr3_get_max_val(spd_val, dimm_num, stat_val);
881 	spd_val = ddr3_div(tmp, ddr_clk_time, 0);
884 	tmp = ddr3_get_max_val(spd_val, dimm_num, stat_val);
1263 u32 ddr3_get_max_val(u32 spd_val, u32 dimm_num, u32 static_val)  argument
1267 		if (spd_val >= static_val)
1268 			return spd_val;
1275 	return spd_val;
1286 u32 ddr3_get_min_val(u32 spd_val, u32 dimm_num, u32 static_val)  argument
1290 		if (spd_val <= static_val)
1291 			return spd_val;
1297 	return spd_val;