Lines Matching refs:info
183 static int ddr3_spd_sum_init(MV_DIMM_INFO *info, MV_DIMM_INFO *sum_info,
187 static int ddr3_spd_init(MV_DIMM_INFO *info, u32 dimm_addr, u32 dimm_width);
240 int ddr3_spd_init(MV_DIMM_INFO *info, u32 dimm_addr, u32 dimm_width) in ddr3_spd_init() argument
262 info->err_check_type = 0; in ddr3_spd_init()
266 info->err_check_type = 1; in ddr3_spd_init()
268 DEBUG_INIT_FULL_C("DRAM err_check_type ", info->err_check_type, 1); in ddr3_spd_init()
272 info->type_info = SPD_MODULE_TYPE_RDIMM; in ddr3_spd_init()
276 info->type_info = SPD_MODULE_TYPE_UDIMM; in ddr3_spd_init()
280 info->type_info = (spd_data[SPD_MODULE_TYPE_BYTE]); in ddr3_spd_init()
287 info->num_of_row_addr = in ddr3_spd_init()
290 info->num_of_row_addr += SPD_ROW_NUM_MIN; in ddr3_spd_init()
291 DEBUG_INIT_FULL_C("DRAM num_of_row_addr ", info->num_of_row_addr, 2); in ddr3_spd_init()
294 info->num_of_col_addr = in ddr3_spd_init()
297 info->num_of_col_addr += SPD_COL_NUM_MIN; in ddr3_spd_init()
298 DEBUG_INIT_FULL_C("DRAM num_of_col_addr ", info->num_of_col_addr, 1); in ddr3_spd_init()
301 info->num_of_module_ranks = in ddr3_spd_init()
304 info->num_of_module_ranks += SPD_MODULE_BANK_NUM_MIN; in ddr3_spd_init()
305 DEBUG_INIT_FULL_C("DRAM numOfModuleBanks ", info->num_of_module_ranks, in ddr3_spd_init()
309 info->data_width = in ddr3_spd_init()
311 DEBUG_INIT_FULL_C("DRAM data_width ", info->data_width, 1); in ddr3_spd_init()
314 info->num_of_banks_on_each_device = in ddr3_spd_init()
317 info->num_of_banks_on_each_device, 1); in ddr3_spd_init()
320 info->sdram_capacity = in ddr3_spd_init()
324 info->sdram_width = 1 << (2 + (spd_data[SPD_MODULE_ORG_BYTE] & in ddr3_spd_init()
326 DEBUG_INIT_FULL_C("DRAM sdram_width ", info->sdram_width, 1); in ddr3_spd_init()
335 info->rank_capacity = in ddr3_spd_init()
336 ((1 << info->sdram_capacity) * 256 * in ddr3_spd_init()
337 (info->data_width / info->sdram_width)) << 16; in ddr3_spd_init()
340 info->rank_capacity = in ddr3_spd_init()
341 ((1 << info->sdram_capacity) * 256 * in ddr3_spd_init()
342 (info->data_width / info->sdram_width) * 0x2) << 16; in ddr3_spd_init()
345 DEBUG_INIT_FULL_C("DRAM rank_capacity[31] ", info->rank_capacity, 1); in ddr3_spd_init()
348 info->num_of_devices = in ddr3_spd_init()
349 ((info->data_width / info->sdram_width) * in ddr3_spd_init()
350 info->num_of_module_ranks) + info->err_check_type; in ddr3_spd_init()
351 DEBUG_INIT_FULL_C("DRAM num_of_devices ", info->num_of_devices, 1); in ddr3_spd_init()
354 info->addr_mirroring = in ddr3_spd_init()
363 info->min_cycle_time = spd_data[SPD_TCK_BYTE] * time_base; in ddr3_spd_init()
364 DEBUG_INIT_FULL_C("DRAM tCKmin ", info->min_cycle_time, 1); in ddr3_spd_init()
372 info->refresh_interval = 7800000; /* Set to 7.8uSec */ in ddr3_spd_init()
373 DEBUG_INIT_FULL_C("DRAM refresh_interval ", info->refresh_interval, 1); in ddr3_spd_init()
389 info->supported_cas_latencies = in ddr3_spd_init()
393 info->supported_cas_latencies, 1); in ddr3_spd_init()
396 info->min_cas_lat_time = (spd_data[SPD_TAA_BYTE] * time_base); in ddr3_spd_init()
406 info->min_write_recovery_time = spd_data[SPD_TWR_BYTE] * time_base; in ddr3_spd_init()
408 info->min_write_recovery_time, 1); in ddr3_spd_init()
411 info->min_ras_to_cas_delay = spd_data[SPD_TRCD_BYTE] * time_base; in ddr3_spd_init()
413 info->min_ras_to_cas_delay, 1); in ddr3_spd_init()
416 info->min_row_active_to_row_active = in ddr3_spd_init()
419 info->min_row_active_to_row_active, 1); in ddr3_spd_init()
422 info->min_row_precharge_time = spd_data[SPD_TRP_BYTE] * time_base; in ddr3_spd_init()
424 info->min_row_precharge_time, 1); in ddr3_spd_init()
427 info->min_active_to_precharge = in ddr3_spd_init()
429 info->min_active_to_precharge |= spd_data[SPD_TRAS_LSB_BYTE]; in ddr3_spd_init()
430 info->min_active_to_precharge *= time_base; in ddr3_spd_init()
432 info->min_active_to_precharge, 1); in ddr3_spd_init()
435 info->min_refresh_recovery = spd_data[SPD_TRFC_MSB_BYTE] << 8; in ddr3_spd_init()
436 info->min_refresh_recovery |= spd_data[SPD_TRFC_LSB_BYTE]; in ddr3_spd_init()
437 info->min_refresh_recovery *= time_base; in ddr3_spd_init()
439 info->min_refresh_recovery, 1); in ddr3_spd_init()
445 info->min_write_to_read_cmd_delay = spd_data[SPD_TWTR_BYTE] * time_base; in ddr3_spd_init()
447 info->min_write_to_read_cmd_delay, 1); in ddr3_spd_init()
453 info->min_read_to_prech_cmd_delay = spd_data[SPD_TRTP_BYTE] * time_base; in ddr3_spd_init()
455 info->min_read_to_prech_cmd_delay, 1); in ddr3_spd_init()
463 info->min_four_active_win_delay = tmp * time_base; in ddr3_spd_init()
465 info->min_four_active_win_delay, 1); in ddr3_spd_init()
469 if (info->type_info == SPD_MODULE_TYPE_RDIMM) { in ddr3_spd_init()
472 info->dimm_rc[rc] = in ddr3_spd_init()
475 info->dimm_rc[rc + 1] = in ddr3_spd_init()
482 info->vendor = (vendor_high << 8) + vendor_low; in ddr3_spd_init()
484 info->vendor, 4); in ddr3_spd_init()
486 info->dimm_rc[0] = RDIMM_RC0; in ddr3_spd_init()
487 info->dimm_rc[1] = RDIMM_RC1; in ddr3_spd_init()
488 info->dimm_rc[2] = RDIMM_RC2; in ddr3_spd_init()
489 info->dimm_rc[8] = RDIMM_RC8; in ddr3_spd_init()
490 info->dimm_rc[9] = RDIMM_RC9; in ddr3_spd_init()
491 info->dimm_rc[10] = RDIMM_RC10; in ddr3_spd_init()
492 info->dimm_rc[11] = RDIMM_RC11; in ddr3_spd_init()
507 int ddr3_spd_sum_init(MV_DIMM_INFO *info, MV_DIMM_INFO *sum_info, u32 dimm) in ddr3_spd_sum_init() argument
510 memcpy(sum_info, info, sizeof(MV_DIMM_INFO)); in ddr3_spd_sum_init()
513 if (sum_info->type_info != info->type_info) { in ddr3_spd_sum_init()
517 if (sum_info->err_check_type > info->err_check_type) { in ddr3_spd_sum_init()
518 sum_info->err_check_type = info->err_check_type; in ddr3_spd_sum_init()
521 if (sum_info->data_width != info->data_width) { in ddr3_spd_sum_init()
525 if (sum_info->min_cycle_time < info->min_cycle_time) in ddr3_spd_sum_init()
526 sum_info->min_cycle_time = info->min_cycle_time; in ddr3_spd_sum_init()
527 if (sum_info->refresh_interval < info->refresh_interval) in ddr3_spd_sum_init()
528 sum_info->refresh_interval = info->refresh_interval; in ddr3_spd_sum_init()
529 sum_info->supported_cas_latencies &= info->supported_cas_latencies; in ddr3_spd_sum_init()
530 if (sum_info->min_cas_lat_time < info->min_cas_lat_time) in ddr3_spd_sum_init()
531 sum_info->min_cas_lat_time = info->min_cas_lat_time; in ddr3_spd_sum_init()
532 if (sum_info->min_write_recovery_time < info->min_write_recovery_time) in ddr3_spd_sum_init()
534 info->min_write_recovery_time; in ddr3_spd_sum_init()
535 if (sum_info->min_ras_to_cas_delay < info->min_ras_to_cas_delay) in ddr3_spd_sum_init()
536 sum_info->min_ras_to_cas_delay = info->min_ras_to_cas_delay; in ddr3_spd_sum_init()
538 info->min_row_active_to_row_active) in ddr3_spd_sum_init()
540 info->min_row_active_to_row_active; in ddr3_spd_sum_init()
541 if (sum_info->min_row_precharge_time < info->min_row_precharge_time) in ddr3_spd_sum_init()
542 sum_info->min_row_precharge_time = info->min_row_precharge_time; in ddr3_spd_sum_init()
543 if (sum_info->min_active_to_precharge < info->min_active_to_precharge) in ddr3_spd_sum_init()
545 info->min_active_to_precharge; in ddr3_spd_sum_init()
546 if (sum_info->min_refresh_recovery < info->min_refresh_recovery) in ddr3_spd_sum_init()
547 sum_info->min_refresh_recovery = info->min_refresh_recovery; in ddr3_spd_sum_init()
549 info->min_write_to_read_cmd_delay) in ddr3_spd_sum_init()
551 info->min_write_to_read_cmd_delay; in ddr3_spd_sum_init()
553 info->min_read_to_prech_cmd_delay) in ddr3_spd_sum_init()
555 info->min_read_to_prech_cmd_delay; in ddr3_spd_sum_init()
557 info->min_four_active_win_delay) in ddr3_spd_sum_init()
559 info->min_four_active_win_delay; in ddr3_spd_sum_init()
561 info->min_write_to_read_cmd_delay) in ddr3_spd_sum_init()
563 info->min_write_to_read_cmd_delay; in ddr3_spd_sum_init()