Lines Matching refs:phase_min
406 u32 phase_min, ui_max_delay; in ddr3_read_leveling_single_cs_rl_mode() local
687 phase_min = 10; in ddr3_read_leveling_single_cs_rl_mode()
690 if (dram_info->rl_val[cs][pup][PS] < phase_min) in ddr3_read_leveling_single_cs_rl_mode()
691 phase_min = dram_info->rl_val[cs][pup][PS]; in ddr3_read_leveling_single_cs_rl_mode()
701 switch (phase_min) { in ddr3_read_leveling_single_cs_rl_mode()
719 add = (add >> (phase_min * REG_TRAINING_DEBUG_3_OFFS)); in ddr3_read_leveling_single_cs_rl_mode()
758 u32 delay_s, delay_e, tmp, phase_min, ui_max_delay; in ddr3_read_leveling_single_cs_window_mode() local
1090 phase_min = 10; in ddr3_read_leveling_single_cs_window_mode()
1126 if (phase < phase_min) /* for the read ready delay */ in ddr3_read_leveling_single_cs_window_mode()
1127 phase_min = phase; in ddr3_read_leveling_single_cs_window_mode()
1141 if (phase < phase_min) /* for the read ready delay */ in ddr3_read_leveling_single_cs_window_mode()
1142 phase_min = phase; in ddr3_read_leveling_single_cs_window_mode()
1165 if (phase < phase_min) /* for the read ready delay */ in ddr3_read_leveling_single_cs_window_mode()
1166 phase_min = phase; in ddr3_read_leveling_single_cs_window_mode()
1176 switch (phase_min) { in ddr3_read_leveling_single_cs_window_mode()
1192 add = (add >> phase_min * REG_TRAINING_DEBUG_3_OFFS); in ddr3_read_leveling_single_cs_window_mode()