Lines Matching refs:dram_info
47 MV_DRAM_INFO *dram_info);
51 MV_DRAM_INFO *dram_info);
62 int ddr3_read_leveling_hw(u32 freq, MV_DRAM_INFO *dram_info) in ddr3_read_leveling_hw() argument
75 reg |= (dram_info->cs_ena << REG_DRAM_TRAINING_CS_OFFS); in ddr3_read_leveling_hw()
94 dram_info->rl_max_phase = 0; in ddr3_read_leveling_hw()
95 dram_info->rl_min_phase = 10; in ddr3_read_leveling_hw()
99 if (dram_info->cs_ena & (1 << cs)) { in ddr3_read_leveling_hw()
101 pup < dram_info->num_of_total_pups; in ddr3_read_leveling_hw()
103 if (pup == dram_info->num_of_std_pups in ddr3_read_leveling_hw()
104 && dram_info->ecc_ena) in ddr3_read_leveling_hw()
112 dram_info->rl_val[cs][pup][P] = phase; in ddr3_read_leveling_hw()
113 if (phase > dram_info->rl_max_phase) in ddr3_read_leveling_hw()
114 dram_info->rl_max_phase = phase; in ddr3_read_leveling_hw()
115 if (phase < dram_info->rl_min_phase) in ddr3_read_leveling_hw()
116 dram_info->rl_min_phase = phase; in ddr3_read_leveling_hw()
117 dram_info->rl_val[cs][pup][D] = delay; in ddr3_read_leveling_hw()
118 dram_info->rl_val[cs][pup][S] = in ddr3_read_leveling_hw()
123 dram_info->rl_val[cs][pup][DQS] = in ddr3_read_leveling_hw()
132 pup < (dram_info->num_of_total_pups); in ddr3_read_leveling_hw()
134 if (pup == dram_info->num_of_std_pups in ddr3_read_leveling_hw()
135 && dram_info->ecc_ena) in ddr3_read_leveling_hw()
140 DEBUG_RL_D((u32) dram_info-> in ddr3_read_leveling_hw()
143 DEBUG_RL_D((u32) dram_info-> in ddr3_read_leveling_hw()
151 dram_info->rd_rdy_dly = in ddr3_read_leveling_hw()
154 dram_info->rd_smpl_dly = in ddr3_read_leveling_hw()
159 dram_info->rd_smpl_dly, 2); in ddr3_read_leveling_hw()
161 dram_info->rd_rdy_dly, 2); in ddr3_read_leveling_hw()
180 int ddr3_read_leveling_sw(u32 freq, int ratio_2to1, MV_DRAM_INFO *dram_info) in ddr3_read_leveling_sw() argument
197 reg = (dram_info->cs_ena << REG_DRAM_TRAINING_CS_OFFS) | in ddr3_read_leveling_sw()
203 for (cs = 0; cs < dram_info->num_cs; cs++) { in ddr3_read_leveling_sw()
206 for (ecc = 0; ecc <= (dram_info->ecc_ena); ecc++) { in ddr3_read_leveling_sw()
210 reg |= (dram_info->ecc_ena * in ddr3_read_leveling_sw()
223 reg |= (dram_info->cl << in ddr3_read_leveling_sw()
233 reg |= ((dram_info->cl + 1) << in ddr3_read_leveling_sw()
237 reg |= ((dram_info->cl + 2) << in ddr3_read_leveling_sw()
248 dram_info); in ddr3_read_leveling_sw()
256 dram_info) in ddr3_read_leveling_sw()
267 pup < (dram_info->num_of_std_pups + dram_info->ecc_ena); in ddr3_read_leveling_sw()
272 DEBUG_RL_D((u32) dram_info->rl_val[cs][pup][P], 1); in ddr3_read_leveling_sw()
274 DEBUG_RL_D((u32) dram_info->rl_val[cs][pup][D], 2); in ddr3_read_leveling_sw()
279 dram_info->rd_smpl_dly, 2); in ddr3_read_leveling_sw()
281 dram_info->rd_rdy_dly, 2); in ddr3_read_leveling_sw()
285 pup < (dram_info->num_of_std_pups + dram_info->ecc_ena); in ddr3_read_leveling_sw()
288 pup_num = (pup == dram_info->num_of_std_pups) ? ECC_BIT : pup; in ddr3_read_leveling_sw()
291 phase = dram_info->rl_val[cs][pup][P]; in ddr3_read_leveling_sw()
292 delay = dram_info->rl_val[cs][pup][D]; in ddr3_read_leveling_sw()
402 MV_DRAM_INFO *dram_info) in ddr3_read_leveling_single_cs_rl_mode() argument
415 rd_sample_delay = dram_info->cl; in ddr3_read_leveling_single_cs_rl_mode()
421 for (pup = 0; pup < (dram_info->num_of_std_pups * (1 - ecc) + ecc); in ddr3_read_leveling_single_cs_rl_mode()
423 dram_info->rl_val[cs][pup + ecc * ECC_BIT][S] = 0; in ddr3_read_leveling_single_cs_rl_mode()
432 DEBUG_RL_FULL_D(dram_info->rd_rdy_dly, 2); in ddr3_read_leveling_single_cs_rl_mode()
460 ddr3_sdram_compare(dram_info, 0xFF, &locked_pups, in ddr3_read_leveling_single_cs_rl_mode()
467 for (pup = 0; pup < (dram_info->num_of_std_pups * (1 - ecc) + ecc); pup++) { in ddr3_read_leveling_single_cs_rl_mode()
471 overrun(cs, dram_info, pup, locked_pups, in ddr3_read_leveling_single_cs_rl_mode()
481 if (locked_sum == (dram_info->num_of_std_pups * in ddr3_read_leveling_single_cs_rl_mode()
577 for (pup = 0; pup < (dram_info->num_of_std_pups * (1 - ecc) + ecc); pup++) { in ddr3_read_leveling_single_cs_rl_mode()
579 if (dram_info->rl_val[cs][idx][S] in ddr3_read_leveling_single_cs_rl_mode()
605 for (pup = 0; pup < (dram_info->num_of_std_pups * (1 - ecc) + ecc); pup++) { in ddr3_read_leveling_single_cs_rl_mode()
607 if (dram_info-> in ddr3_read_leveling_single_cs_rl_mode()
673 dram_info->rd_smpl_dly = rd_sample_delay; in ddr3_read_leveling_single_cs_rl_mode()
674 dram_info->rd_rdy_dly = rd_sample_delay + add; in ddr3_read_leveling_single_cs_rl_mode()
679 (dram_info->num_of_std_pups * (1 - ecc) + ecc); in ddr3_read_leveling_single_cs_rl_mode()
681 if (dram_info->rl_val[cs][idx][C] < RL_RETRY_COUNT) in ddr3_read_leveling_single_cs_rl_mode()
682 dram_info->rl_val[cs][idx][C] = 0; in ddr3_read_leveling_single_cs_rl_mode()
689 for (pup = 0; pup < (dram_info->num_of_std_pups); pup++) { in ddr3_read_leveling_single_cs_rl_mode()
690 if (dram_info->rl_val[cs][pup][PS] < phase_min) in ddr3_read_leveling_single_cs_rl_mode()
691 phase_min = dram_info->rl_val[cs][pup][PS]; in ddr3_read_leveling_single_cs_rl_mode()
728 dram_info->rd_rdy_dly = rd_sample_delay + add; in ddr3_read_leveling_single_cs_rl_mode()
730 for (cs = 0; cs < dram_info->num_cs; cs++) { in ddr3_read_leveling_single_cs_rl_mode()
731 for (pup = 0; pup < dram_info->num_of_total_pups; pup++) { in ddr3_read_leveling_single_cs_rl_mode()
733 dram_info->rl_val[cs][pup][DQS] = (reg & 0x3F); in ddr3_read_leveling_single_cs_rl_mode()
754 MV_DRAM_INFO *dram_info) in ddr3_read_leveling_single_cs_window_mode() argument
767 rd_sample_delay = dram_info->cl; in ddr3_read_leveling_single_cs_window_mode()
775 for (pup = 0; pup < (dram_info->num_of_std_pups * (1 - ecc) + ecc); in ddr3_read_leveling_single_cs_window_mode()
777 dram_info->rl_val[cs][pup + ecc * ECC_BIT][S] = 0; in ddr3_read_leveling_single_cs_window_mode()
786 DEBUG_RL_FULL_D(dram_info->rd_rdy_dly, 2); in ddr3_read_leveling_single_cs_window_mode()
814 ddr3_sdram_compare(dram_info, 0xFF, &locked_pups, in ddr3_read_leveling_single_cs_window_mode()
820 for (pup = 0; pup < (dram_info->num_of_std_pups * in ddr3_read_leveling_single_cs_window_mode()
834 if (dram_info->rl_val[cs][idx][S] == RL_WINDOW_STATE) { in ddr3_read_leveling_single_cs_window_mode()
847 dram_info->rl_val[cs][idx][DE] = delay; in ddr3_read_leveling_single_cs_window_mode()
848 dram_info->rl_val[cs][idx][PE] = phase; in ddr3_read_leveling_single_cs_window_mode()
850 dram_info->rl_val[cs][idx][S]++; in ddr3_read_leveling_single_cs_window_mode()
857 } else if (dram_info->rl_val[cs][idx][S] == in ddr3_read_leveling_single_cs_window_mode()
864 if (dram_info->rl_val[cs][idx][C] < in ddr3_read_leveling_single_cs_window_mode()
870 dram_info->rl_val[cs][idx][C]++; in ddr3_read_leveling_single_cs_window_mode()
873 if (dram_info->rl_val[cs][idx][C] == in ddr3_read_leveling_single_cs_window_mode()
875 dram_info->rl_val[cs][idx][C] = 0; in ddr3_read_leveling_single_cs_window_mode()
876 dram_info->rl_val[cs][idx][DS] = in ddr3_read_leveling_single_cs_window_mode()
878 dram_info->rl_val[cs][idx][PS] = in ddr3_read_leveling_single_cs_window_mode()
880 dram_info->rl_val[cs][idx][S]++; /* Go to Window State */ in ddr3_read_leveling_single_cs_window_mode()
909 if (final_sum == (dram_info->num_of_std_pups * (1 - ecc) + ecc)) { in ddr3_read_leveling_single_cs_window_mode()
1075 dram_info->rd_smpl_dly = rd_sample_delay; in ddr3_read_leveling_single_cs_window_mode()
1076 dram_info->rd_rdy_dly = rd_sample_delay + add; in ddr3_read_leveling_single_cs_window_mode()
1082 (dram_info->num_of_std_pups * (1 - ecc) + ecc); in ddr3_read_leveling_single_cs_window_mode()
1084 if (dram_info->rl_val[cs][idx][C] < RL_RETRY_COUNT) in ddr3_read_leveling_single_cs_window_mode()
1085 dram_info->rl_val[cs][idx][C] = 0; in ddr3_read_leveling_single_cs_window_mode()
1092 for (pup = 0; pup < (dram_info->num_of_std_pups); pup++) { in ddr3_read_leveling_single_cs_window_mode()
1096 DEBUG_RL_D((u32) dram_info->rl_val[cs][pup][PS], 1); in ddr3_read_leveling_single_cs_window_mode()
1098 DEBUG_RL_D((u32) dram_info->rl_val[cs][pup][DS], 2); in ddr3_read_leveling_single_cs_window_mode()
1100 DEBUG_RL_D((u32) dram_info->rl_val[cs][pup][PE], 1); in ddr3_read_leveling_single_cs_window_mode()
1102 DEBUG_RL_D((u32) dram_info->rl_val[cs][pup][DE], 2); in ddr3_read_leveling_single_cs_window_mode()
1107 for (pup = 0; pup < (dram_info->num_of_std_pups * (1 - ecc) + ecc); in ddr3_read_leveling_single_cs_window_mode()
1111 if (dram_info->rl_val[cs][idx][PS] == 4) in ddr3_read_leveling_single_cs_window_mode()
1112 dram_info->rl_val[cs][idx][PS] = 1; in ddr3_read_leveling_single_cs_window_mode()
1113 if (dram_info->rl_val[cs][idx][PE] == 4) in ddr3_read_leveling_single_cs_window_mode()
1114 dram_info->rl_val[cs][idx][PE] = 1; in ddr3_read_leveling_single_cs_window_mode()
1116 delay_s = dram_info->rl_val[cs][idx][PS] * in ddr3_read_leveling_single_cs_window_mode()
1117 MAX_DELAY_INV + dram_info->rl_val[cs][idx][DS]; in ddr3_read_leveling_single_cs_window_mode()
1118 delay_e = dram_info->rl_val[cs][idx][PE] * in ddr3_read_leveling_single_cs_window_mode()
1119 MAX_DELAY_INV + dram_info->rl_val[cs][idx][DE]; in ddr3_read_leveling_single_cs_window_mode()
1129 dram_info->rl_val[cs][idx][P] = phase; in ddr3_read_leveling_single_cs_window_mode()
1130 dram_info->rl_val[cs][idx][D] = tmp % MAX_DELAY_INV; in ddr3_read_leveling_single_cs_window_mode()
1133 delay_s = dram_info->rl_val[cs][idx][PS] * in ddr3_read_leveling_single_cs_window_mode()
1134 MAX_DELAY + dram_info->rl_val[cs][idx][DS]; in ddr3_read_leveling_single_cs_window_mode()
1135 delay_e = dram_info->rl_val[cs][idx][PE] * in ddr3_read_leveling_single_cs_window_mode()
1136 MAX_DELAY + dram_info->rl_val[cs][idx][DE]; in ddr3_read_leveling_single_cs_window_mode()
1144 dram_info->rl_val[cs][idx][P] = phase; in ddr3_read_leveling_single_cs_window_mode()
1145 dram_info->rl_val[cs][idx][D] = tmp % MAX_DELAY; in ddr3_read_leveling_single_cs_window_mode()
1149 if (dram_info->rl_val[cs][idx][PS] > 1) in ddr3_read_leveling_single_cs_window_mode()
1150 dram_info->rl_val[cs][idx][PS] -= 2; in ddr3_read_leveling_single_cs_window_mode()
1151 if (dram_info->rl_val[cs][idx][PE] > 1) in ddr3_read_leveling_single_cs_window_mode()
1152 dram_info->rl_val[cs][idx][PE] -= 2; in ddr3_read_leveling_single_cs_window_mode()
1155 delay_s = dram_info->rl_val[cs][idx][PS] * MAX_DELAY + in ddr3_read_leveling_single_cs_window_mode()
1156 dram_info->rl_val[cs][idx][DS]; in ddr3_read_leveling_single_cs_window_mode()
1157 delay_e = dram_info->rl_val[cs][idx][PE] * MAX_DELAY + in ddr3_read_leveling_single_cs_window_mode()
1158 dram_info->rl_val[cs][idx][DE]; in ddr3_read_leveling_single_cs_window_mode()
1168 dram_info->rl_val[cs][idx][P] = phase; in ddr3_read_leveling_single_cs_window_mode()
1169 dram_info->rl_val[cs][idx][D] = tmp % MAX_DELAY; in ddr3_read_leveling_single_cs_window_mode()
1203 dram_info->rd_rdy_dly = rd_sample_delay + add; in ddr3_read_leveling_single_cs_window_mode()
1205 for (cs = 0; cs < dram_info->num_cs; cs++) { in ddr3_read_leveling_single_cs_window_mode()
1206 for (pup = 0; pup < dram_info->num_of_total_pups; pup++) { in ddr3_read_leveling_single_cs_window_mode()
1208 dram_info->rl_val[cs][pup][DQS] = (reg & 0x3F); in ddr3_read_leveling_single_cs_window_mode()