Lines Matching refs:add
404 u32 reg, delay, phase, pup, rd_sample_delay, add, locked_pups, in ddr3_read_leveling_single_cs_rl_mode() local
635 add = reg_read(REG_TRAINING_DEBUG_2_ADDR); in ddr3_read_leveling_single_cs_rl_mode()
638 add = (add >> in ddr3_read_leveling_single_cs_rl_mode()
642 add = (add >> in ddr3_read_leveling_single_cs_rl_mode()
647 add = (add >> in ddr3_read_leveling_single_cs_rl_mode()
652 add = (add >> in ddr3_read_leveling_single_cs_rl_mode()
657 add &= REG_TRAINING_DEBUG_2_MASK; in ddr3_read_leveling_single_cs_rl_mode()
660 add = reg_read(REG_TRAINING_DEBUG_3_ADDR); in ddr3_read_leveling_single_cs_rl_mode()
661 add = (add >> in ddr3_read_leveling_single_cs_rl_mode()
664 add &= REG_TRAINING_DEBUG_3_MASK; in ddr3_read_leveling_single_cs_rl_mode()
670 reg |= ((rd_sample_delay + add) << in ddr3_read_leveling_single_cs_rl_mode()
674 dram_info->rd_rdy_dly = rd_sample_delay + add; in ddr3_read_leveling_single_cs_rl_mode()
700 add = reg_read(REG_TRAINING_DEBUG_2_ADDR); in ddr3_read_leveling_single_cs_rl_mode()
703 add = (add >> REG_TRAINING_DEBUG_2_OFFS); in ddr3_read_leveling_single_cs_rl_mode()
706 add = (add >> (REG_TRAINING_DEBUG_2_OFFS + 3)); in ddr3_read_leveling_single_cs_rl_mode()
709 add = (add >> (REG_TRAINING_DEBUG_2_OFFS + 6)); in ddr3_read_leveling_single_cs_rl_mode()
712 add = (add >> (REG_TRAINING_DEBUG_2_OFFS + 9)); in ddr3_read_leveling_single_cs_rl_mode()
715 add &= REG_TRAINING_DEBUG_2_MASK; in ddr3_read_leveling_single_cs_rl_mode()
718 add = reg_read(REG_TRAINING_DEBUG_3_ADDR); in ddr3_read_leveling_single_cs_rl_mode()
719 add = (add >> (phase_min * REG_TRAINING_DEBUG_3_OFFS)); in ddr3_read_leveling_single_cs_rl_mode()
720 add &= REG_TRAINING_DEBUG_3_MASK; in ddr3_read_leveling_single_cs_rl_mode()
726 reg |= ((rd_sample_delay + add) << (REG_READ_DATA_READY_DELAYS_OFFS * cs)); in ddr3_read_leveling_single_cs_rl_mode()
728 dram_info->rd_rdy_dly = rd_sample_delay + add; in ddr3_read_leveling_single_cs_rl_mode()
756 u32 reg, delay, phase, sum, pup, rd_sample_delay, add, locked_pups, in ddr3_read_leveling_single_cs_window_mode() local
1040 add = reg_read(REG_TRAINING_DEBUG_2_ADDR); in ddr3_read_leveling_single_cs_window_mode()
1043 add = add >> in ddr3_read_leveling_single_cs_window_mode()
1047 add = add >> in ddr3_read_leveling_single_cs_window_mode()
1052 add = add >> in ddr3_read_leveling_single_cs_window_mode()
1057 add = add >> in ddr3_read_leveling_single_cs_window_mode()
1064 add = reg_read(REG_TRAINING_DEBUG_3_ADDR); in ddr3_read_leveling_single_cs_window_mode()
1065 add = (add >> phase * in ddr3_read_leveling_single_cs_window_mode()
1068 add &= REG_TRAINING_DEBUG_2_MASK; in ddr3_read_leveling_single_cs_window_mode()
1072 reg |= ((rd_sample_delay + add) << in ddr3_read_leveling_single_cs_window_mode()
1076 dram_info->rd_rdy_dly = rd_sample_delay + add; in ddr3_read_leveling_single_cs_window_mode()
1175 add = reg_read(REG_TRAINING_DEBUG_2_ADDR); in ddr3_read_leveling_single_cs_window_mode()
1178 add = (add >> REG_TRAINING_DEBUG_2_OFFS); in ddr3_read_leveling_single_cs_window_mode()
1181 add = (add >> (REG_TRAINING_DEBUG_2_OFFS + 3)); in ddr3_read_leveling_single_cs_window_mode()
1184 add = (add >> (REG_TRAINING_DEBUG_2_OFFS + 6)); in ddr3_read_leveling_single_cs_window_mode()
1187 add = (add >> (REG_TRAINING_DEBUG_2_OFFS + 9)); in ddr3_read_leveling_single_cs_window_mode()
1191 add = reg_read(REG_TRAINING_DEBUG_3_ADDR); in ddr3_read_leveling_single_cs_window_mode()
1192 add = (add >> phase_min * REG_TRAINING_DEBUG_3_OFFS); in ddr3_read_leveling_single_cs_window_mode()
1195 add &= REG_TRAINING_DEBUG_2_MASK; in ddr3_read_leveling_single_cs_window_mode()
1201 ((rd_sample_delay + add) << (REG_READ_DATA_READY_DELAYS_OFFS * cs)); in ddr3_read_leveling_single_cs_window_mode()
1203 dram_info->rd_rdy_dly = rd_sample_delay + add; in ddr3_read_leveling_single_cs_window_mode()