Lines Matching refs:skew_array
43 static u32 skew_array[(MAX_PUP_NUM) * DQ_NUM] = { 0 }; variable
265 DEBUG_PBS_D(skew_array in ddr3_pbs_tx()
280 [dq] += skew_array in ddr3_pbs_tx()
340 skew_array[((pup) * DQ_NUM) + dq] = in ddr3_pbs_tx()
364 DEBUG_PBS_D(skew_array[(pup * DQ_NUM) + dq], 2); in ddr3_pbs_tx()
776 DEBUG_PBS_FULL_D(skew_array in ddr3_pbs_rx()
794 skew_array[((pup) * DQ_NUM) + dq]; in ddr3_pbs_rx()
856 skew_array[((pup) * DQ_NUM) + dq] = in ddr3_pbs_rx()
880 DEBUG_PBS_D(skew_array[(pup * DQ_NUM) + dq], 2); in ddr3_pbs_rx()
1107 skew_array[(pup * DQ_NUM) + dq] = pbs_curr_val; in lock_pups()
1172 memset(&skew_array, 0, MAX_PUP_NUM * DQ_NUM * sizeof(u32)); in ddr3_pbs_per_bit()
1244 skew_array, in ddr3_pbs_per_bit()
1338 skew_array[((pup) * in ddr3_pbs_per_bit()
1442 if (pbs_min > skew_array[(pup * DQ_NUM) + dq]) in ddr3_set_pbs_results()
1443 pbs_min = skew_array[(pup * DQ_NUM) + dq]; in ddr3_set_pbs_results()
1445 if (pbs_max < skew_array[(pup * DQ_NUM) + dq]) in ddr3_set_pbs_results()
1446 pbs_max = skew_array[(pup * DQ_NUM) + dq]; in ddr3_set_pbs_results()
1473 DEBUG_PBS_FULL_D((skew_array[(pup * DQ_NUM) + dq] - in ddr3_set_pbs_results()
1486 skew_array[idx] - pbs_min); in ddr3_set_pbs_results()
1489 val[pup] += skew_array[idx] - pbs_min; in ddr3_set_pbs_results()