701 	u32 *sdram_offset = (u32 *)RESUME_TRAINING_VALUES_ADDR;  in ddr3_save_training()  local
745 							(*sdram_offset) = val;  in ddr3_save_training()
746 							crc += *sdram_offset;  in ddr3_save_training()
747 							sdram_offset++;  in ddr3_save_training()
756 					*sdram_offset = val;  in ddr3_save_training()
757 					crc += *sdram_offset;  in ddr3_save_training()
758 					sdram_offset++;  in ddr3_save_training()
765 	*sdram_offset = reg_read(REG_READ_DATA_SAMPLE_DELAYS_ADDR);  in ddr3_save_training()
766 	crc += *sdram_offset;  in ddr3_save_training()
767 	sdram_offset++;  in ddr3_save_training()
769 	*sdram_offset = reg_read(REG_READ_DATA_READY_DELAYS_ADDR);  in ddr3_save_training()
770 	crc += *sdram_offset;  in ddr3_save_training()
771 	sdram_offset++;  in ddr3_save_training()
773 	sdram_offset = (u32 *)NUM_OF_REGISTER_ADDR;  in ddr3_save_training()
774 	*sdram_offset = regs;  in ddr3_save_training()
778 	sdram_offset = (u32 *)CHECKSUM_RESULT_ADDR;  in ddr3_save_training()
779 	*sdram_offset = crc;  in ddr3_save_training()
794 	u32 *sdram_offset = (u32 *)RESUME_TRAINING_VALUES_ADDR;  in ddr3_read_training_results()  local
803 		training_val[idx] = *sdram_offset;  in ddr3_read_training_results()
804 		crc += *sdram_offset;  in ddr3_read_training_results()
805 		sdram_offset++;  in ddr3_read_training_results()
808 	sdram_offset = (u32 *)CHECKSUM_RESULT_ADDR;  in ddr3_read_training_results()
810 	if ((*sdram_offset) == crc) {  in ddr3_read_training_results()
873 	u32 *sdram_offset = (u32 *)BOOT_INFO_ADDR;  in ddr3_check_if_resume_mode()  local
903 	magic_word = *sdram_offset;  in ddr3_check_if_resume_mode()