31 static int ddr3_tip_wl_supp_align_err_shift(u32 dev_num, u32 if_id, u32 bus_id,
34 					      u32 bus_id, u32 offset,
36 static int ddr3_tip_xsb_compare_test(u32 dev_num, u32 if_id, u32 bus_id,
39 					      u32 bus_id, u32 bus_id_delta);
1308 	u32 if_id, bus_id, data, data_tmp;  in ddr3_tip_dynamic_write_leveling_supp()  local
1316 		for (bus_id = 0; bus_id < GET_TOPOLOGY_NUM_OF_BUSES();  in ddr3_tip_dynamic_write_leveling_supp()
1317 		     bus_id++) {  in ddr3_tip_dynamic_write_leveling_supp()
1318 			VALIDATE_ACTIVE(tm->bus_act_mask, bus_id);  in ddr3_tip_dynamic_write_leveling_supp()
1319 			wr_supp_res[if_id][bus_id].is_pup_fail = 1;  in ddr3_tip_dynamic_write_leveling_supp()
1322 				      bus_id, DDR_PHY_DATA,  in ddr3_tip_dynamic_write_leveling_supp()
1331 			    (dev_num, if_id, bus_id, 0, 0) == MV_OK) {  in ddr3_tip_dynamic_write_leveling_supp()
1335 					 if_id, bus_id));  in ddr3_tip_dynamic_write_leveling_supp()
1343 				      ACCESS_TYPE_UNICAST, bus_id, DDR_PHY_DATA,  in ddr3_tip_dynamic_write_leveling_supp()
1349 				      bus_id, DDR_PHY_DATA,  in ddr3_tip_dynamic_write_leveling_supp()
1359 			    (dev_num, if_id, bus_id, adll_offset, 0) == MV_OK) {  in ddr3_tip_dynamic_write_leveling_supp()
1363 					 if_id, bus_id, adll_offset));  in ddr3_tip_dynamic_write_leveling_supp()
1371 				      ACCESS_TYPE_UNICAST, bus_id, DDR_PHY_DATA,  in ddr3_tip_dynamic_write_leveling_supp()
1377 				      bus_id, DDR_PHY_DATA,  in ddr3_tip_dynamic_write_leveling_supp()
1386 			    (dev_num, if_id, bus_id, adll_offset, 0) == MV_OK) {  in ddr3_tip_dynamic_write_leveling_supp()
1390 					 if_id, bus_id, adll_offset));  in ddr3_tip_dynamic_write_leveling_supp()
1396 					 if_id, bus_id));  in ddr3_tip_dynamic_write_leveling_supp()
1402 				if_id, bus_id, is_if_fail));  in ddr3_tip_dynamic_write_leveling_supp()
1426 					      u32 bus_id, u32 offset,  in ddr3_tip_wl_supp_align_phase_shift()  argument
1429 	wr_supp_res[if_id][bus_id].stage = PHASE_SHIFT;  in ddr3_tip_wl_supp_align_phase_shift()
1430 	if (ddr3_tip_xsb_compare_test(dev_num, if_id, bus_id,  in ddr3_tip_wl_supp_align_phase_shift()
1432 		wr_supp_res[if_id][bus_id].is_pup_fail = 0;  in ddr3_tip_wl_supp_align_phase_shift()
1434 	} else if (ddr3_tip_xsb_compare_test(dev_num, if_id, bus_id,  in ddr3_tip_wl_supp_align_phase_shift()
1438 		wr_supp_res[if_id][bus_id].stage = CLOCK_SHIFT;  in ddr3_tip_wl_supp_align_phase_shift()
1441 				if_id, bus_id, offset));  in ddr3_tip_wl_supp_align_phase_shift()
1442 		ddr3_tip_wl_supp_one_clk_err_shift(dev_num, if_id, bus_id, 0);  in ddr3_tip_wl_supp_align_phase_shift()
1443 		wr_supp_res[if_id][bus_id].is_pup_fail = 0;  in ddr3_tip_wl_supp_align_phase_shift()
1445 	} else if (ddr3_tip_xsb_compare_test(dev_num, if_id, bus_id,  in ddr3_tip_wl_supp_align_phase_shift()
1451 				if_id, bus_id, offset));  in ddr3_tip_wl_supp_align_phase_shift()
1452 		wr_supp_res[if_id][bus_id].stage = ALIGN_SHIFT;  in ddr3_tip_wl_supp_align_phase_shift()
1453 		ddr3_tip_wl_supp_align_err_shift(dev_num, if_id, bus_id, 0);  in ddr3_tip_wl_supp_align_phase_shift()
1454 		wr_supp_res[if_id][bus_id].is_pup_fail = 0;  in ddr3_tip_wl_supp_align_phase_shift()
1457 		wr_supp_res[if_id][bus_id].is_pup_fail = 1;  in ddr3_tip_wl_supp_align_phase_shift()
1465 static int ddr3_tip_xsb_compare_test(u32 dev_num, u32 if_id, u32 bus_id,  in ddr3_tip_xsb_compare_test()  argument
1496 		 if_id, bus_id, read_pattern[0], read_pattern[1],  in ddr3_tip_xsb_compare_test()
1509 		if ((read_pattern[word_in_pattern] & pup_mask_table[bus_id]) ==  in ddr3_tip_xsb_compare_test()
1511 		     pup_mask_table[bus_id]))  in ddr3_tip_xsb_compare_test()
1521 			 if_id, bus_id, num_of_succ_byte_compare));  in ddr3_tip_xsb_compare_test()
1527 			 if_id, bus_id, num_of_succ_byte_compare));  in ddr3_tip_xsb_compare_test()
1551 			 if_id, bus_id, num_of_succ_byte_compare));  in ddr3_tip_xsb_compare_test()
1561 					      u32 bus_id, u32 bus_id_delta)  in ddr3_tip_wl_supp_one_clk_err_shift()  argument
1568 		     (dev_num, if_id, ACCESS_TYPE_UNICAST, bus_id,  in ddr3_tip_wl_supp_one_clk_err_shift()
1574 			if_id, bus_id, phase, adll));  in ddr3_tip_wl_supp_one_clk_err_shift()
1578 			     (dev_num, ACCESS_TYPE_UNICAST, if_id, bus_id,  in ddr3_tip_wl_supp_one_clk_err_shift()
1585 				      bus_id, DDR_PHY_DATA, 0, data,  in ddr3_tip_wl_supp_one_clk_err_shift()
1590 				      bus_id, DDR_PHY_DATA, 1, data, 0x3f));  in ddr3_tip_wl_supp_one_clk_err_shift()
1604 					    u32 bus_id, u32 bus_id_delta)  in ddr3_tip_wl_supp_align_err_shift()  argument
1611 				       bus_id, DDR_PHY_DATA, WL_PHY_REG,  in ddr3_tip_wl_supp_align_err_shift()
1618 		 if_id, bus_id, phase, adll));  in ddr3_tip_wl_supp_align_err_shift()
1629 					      if_id, bus_id, DDR_PHY_DATA,  in ddr3_tip_wl_supp_align_err_shift()
1634 					      if_id, bus_id, DDR_PHY_DATA,  in ddr3_tip_wl_supp_align_err_shift()
1645 			     (dev_num, ACCESS_TYPE_UNICAST, if_id, bus_id,  in ddr3_tip_wl_supp_align_err_shift()
1663 	u32 bus_id, dq_id;  in ddr3_tip_dynamic_write_leveling_seq()  local
1702 	for (bus_id = 0; bus_id < tm->num_of_bus_per_interface; bus_id++) {  in ddr3_tip_dynamic_write_leveling_seq()
1705 			      mask_results_pup_reg_map[bus_id], 0x1 << 24,  in ddr3_tip_dynamic_write_leveling_seq()
1710 	for (bus_id = 0; bus_id < tm->num_of_bus_per_interface; bus_id++) {  in ddr3_tip_dynamic_write_leveling_seq()
1711 		VALIDATE_ACTIVE(tm->bus_act_mask, bus_id);  in ddr3_tip_dynamic_write_leveling_seq()
1714 			      mask_results_pup_reg_map[bus_id], 0, 0x1 << 24));  in ddr3_tip_dynamic_write_leveling_seq()
1729 	u32 bus_id, dq_id;  in ddr3_tip_dynamic_read_leveling_seq()  local
1743 	for (bus_id = 0; bus_id < tm->num_of_bus_per_interface; bus_id++) {  in ddr3_tip_dynamic_read_leveling_seq()
1746 			      mask_results_pup_reg_map[bus_id], 0x1 << 24,  in ddr3_tip_dynamic_read_leveling_seq()
1751 	for (bus_id = 0; bus_id < tm->num_of_bus_per_interface; bus_id++) {  in ddr3_tip_dynamic_read_leveling_seq()
1752 		VALIDATE_ACTIVE(tm->bus_act_mask, bus_id);  in ddr3_tip_dynamic_read_leveling_seq()
1755 			      mask_results_pup_reg_map[bus_id], 0, 0x1 << 24));  in ddr3_tip_dynamic_read_leveling_seq()
1766 	u32 bus_id, dq_id;  in ddr3_tip_dynamic_per_bit_read_leveling_seq()  local
1780 	for (bus_id = 0; bus_id < tm->num_of_bus_per_interface; bus_id++) {  in ddr3_tip_dynamic_per_bit_read_leveling_seq()
1783 			      mask_results_pup_reg_map[bus_id], 0x1 << 24,  in ddr3_tip_dynamic_per_bit_read_leveling_seq()
1804 	u32 bus_id = 0, if_id = 0;  in ddr3_tip_print_wl_supp_result()  local
1812 		for (bus_id = 0; bus_id < tm->num_of_bus_per_interface;  in ddr3_tip_print_wl_supp_result()
1813 		     bus_id++) {  in ddr3_tip_print_wl_supp_result()
1814 			VALIDATE_ACTIVE(tm->bus_act_mask, bus_id);  in ddr3_tip_print_wl_supp_result()
1817 					[bus_id].is_pup_fail));  in ddr3_tip_print_wl_supp_result()
1826 		for (bus_id = 0; bus_id < tm->num_of_bus_per_interface;  in ddr3_tip_print_wl_supp_result()
1827 		     bus_id++) {  in ddr3_tip_print_wl_supp_result()
1828 			VALIDATE_ACTIVE(tm->bus_act_mask, bus_id);  in ddr3_tip_print_wl_supp_result()
1831 					[bus_id].stage));  in ddr3_tip_print_wl_supp_result()