103 			     MAX_POLLING_ITERATIONS) != MV_OK) {  in ddr3_tip_dynamic_read_leveling()
147 		return MV_OK;  in ddr3_tip_dynamic_read_leveling()
287 		     MAX_POLLING_ITERATIONS) != MV_OK) {  in ddr3_tip_dynamic_read_leveling()
314 		     ODPG_ENABLE_REG, MAX_POLLING_ITERATIONS) != MV_OK) {  in ddr3_tip_dynamic_read_leveling()
336 				     MAX_POLLING_ITERATIONS) != MV_OK) {  in ddr3_tip_dynamic_read_leveling()
435 	return MV_OK;  in ddr3_tip_dynamic_read_leveling()
469 		     MAX_POLLING_ITERATIONS) != MV_OK) {  in ddr3_tip_legacy_dynamic_write_leveling()
476 	return MV_OK;  in ddr3_tip_legacy_dynamic_write_leveling()
510 		     MAX_POLLING_ITERATIONS) != MV_OK) {  in ddr3_tip_legacy_dynamic_read_leveling()
517 	return MV_OK;  in ddr3_tip_legacy_dynamic_read_leveling()
686 		     MAX_POLLING_ITERATIONS) != MV_OK) {  in ddr3_tip_dynamic_per_bit_read_leveling()
713 		     ODPG_ENABLE_REG, MAX_POLLING_ITERATIONS) != MV_OK) {  in ddr3_tip_dynamic_per_bit_read_leveling()
744 						    MV_OK) {  in ddr3_tip_dynamic_per_bit_read_leveling()
914 	return MV_OK;  in ddr3_tip_dynamic_per_bit_read_leveling()
951 	return MV_OK;  in ddr3_tip_calc_cs_mask()
1014 		     SDRAM_OPERATION_REG, MAX_POLLING_ITERATIONS) != MV_OK) {  in ddr3_tip_dynamic_write_leveling()
1063 			     MAX_POLLING_ITERATIONS) != MV_OK) {  in ddr3_tip_dynamic_write_leveling()
1092 			     MAX_POLLING_ITERATIONS) != MV_OK) {  in ddr3_tip_dynamic_write_leveling()
1299 	return MV_OK;  in ddr3_tip_dynamic_write_leveling()
1331 			    (dev_num, if_id, bus_id, 0, 0) == MV_OK) {  in ddr3_tip_dynamic_write_leveling_supp()
1359 			    (dev_num, if_id, bus_id, adll_offset, 0) == MV_OK) {  in ddr3_tip_dynamic_write_leveling_supp()
1386 			    (dev_num, if_id, bus_id, adll_offset, 0) == MV_OK) {  in ddr3_tip_dynamic_write_leveling_supp()
1419 	return MV_OK;  in ddr3_tip_dynamic_write_leveling_supp()
1431 				      0, bus_id_delta) == MV_OK) {  in ddr3_tip_wl_supp_align_phase_shift()
1433 		return MV_OK;  in ddr3_tip_wl_supp_align_phase_shift()
1436 					     bus_id_delta) == MV_OK) {  in ddr3_tip_wl_supp_align_phase_shift()
1444 		return MV_OK;  in ddr3_tip_wl_supp_align_phase_shift()
1447 					     bus_id_delta) == MV_OK) {  in ddr3_tip_wl_supp_align_phase_shift()
1455 		return MV_OK;  in ddr3_tip_wl_supp_align_phase_shift()
1522 		return MV_OK;  in ddr3_tip_xsb_compare_test()
1597 	return MV_OK;  in ddr3_tip_wl_supp_one_clk_err_shift()
1636 				return MV_OK;  in ddr3_tip_wl_supp_align_err_shift()
1647 		return MV_OK;  in ddr3_tip_wl_supp_align_err_shift()
1655 	return MV_OK;  in ddr3_tip_wl_supp_align_err_shift()
1721 	return MV_OK;  in ddr3_tip_dynamic_write_leveling_seq()
1758 	return MV_OK;  in ddr3_tip_dynamic_read_leveling_seq()
1796 	return MV_OK;  in ddr3_tip_dynamic_per_bit_read_leveling_seq()
1835 	return MV_OK;  in ddr3_tip_print_wl_supp_result()