Lines Matching refs:tm
211 struct hws_topology_map *tm = ddr3_get_topology_map(); in ddr3_tip_configure_cs() local
214 data = (tm->interface_params[if_id].bus_width == in ddr3_tip_configure_cs()
220 mem_index = tm->interface_params[if_id].memory_size; in ddr3_tip_configure_cs()
270 struct hws_topology_map *tm = ddr3_get_topology_map(); in calc_cs_num() local
273 VALIDATE_ACTIVE(tm->bus_act_mask, bus_cnt); in calc_cs_num()
275 cs_bitmask = tm->interface_params[if_id]. in calc_cs_num()
317 struct hws_topology_map *tm = ddr3_get_topology_map(); in hws_ddr3_tip_init_controller() local
330 VALIDATE_ACTIVE(tm->if_act_mask, if_id); in hws_ddr3_tip_init_controller()
337 VALIDATE_ACTIVE(tm->bus_act_mask, bus_index); in hws_ddr3_tip_init_controller()
339 tm->interface_params[if_id]. in hws_ddr3_tip_init_controller()
351 tm->interface_params[if_id]. in hws_ddr3_tip_init_controller()
354 tm->interface_params[if_id]. in hws_ddr3_tip_init_controller()
358 (tm->interface_params[if_id]. in hws_ddr3_tip_init_controller()
373 (DDR3_IS_16BIT_DRAM_MODE(tm->bus_act_mask) in hws_ddr3_tip_init_controller()
444 (tm->interface_params[if_id]. in hws_ddr3_tip_init_controller()
464 (tm->interface_params[if_id]. in hws_ddr3_tip_init_controller()
471 VALIDATE_ACTIVE(tm->bus_act_mask, bus_cnt); in hws_ddr3_tip_init_controller()
473 tm->interface_params[if_id]. in hws_ddr3_tip_init_controller()
502 tm->interface_params[if_id]. in hws_ddr3_tip_init_controller()
505 tm->interface_params[if_id]. in hws_ddr3_tip_init_controller()
540 ((tm->interface_params[if_id]. in hws_ddr3_tip_init_controller()
573 timing = tm->interface_params[if_id].timing; in hws_ddr3_tip_init_controller()
641 VALIDATE_ACTIVE(tm->if_act_mask, if_id); in hws_ddr3_tip_init_controller()
671 int hws_ddr3_tip_load_topology_map(u32 dev_num, struct hws_topology_map *tm) in hws_ddr3_tip_load_topology_map() argument
678 tm = ddr3_get_topology_map(); in hws_ddr3_tip_load_topology_map()
680 ((u8)dev_num, tm->if_act_mask, in hws_ddr3_tip_load_topology_map()
684 tm->if_act_mask, in hws_ddr3_tip_load_topology_map()
685 tm->num_of_bus_per_interface)); in hws_ddr3_tip_load_topology_map()
692 VALIDATE_ACTIVE(tm->if_act_mask, if_id); in hws_ddr3_tip_load_topology_map()
694 tm->interface_params[if_id].speed_bin_index; in hws_ddr3_tip_load_topology_map()
696 freq = tm->interface_params[first_active_if].memory_freq; in hws_ddr3_tip_load_topology_map()
701 tm->interface_params[if_id]. in hws_ddr3_tip_load_topology_map()
703 tm->interface_params[if_id]. in hws_ddr3_tip_load_topology_map()
706 if (tm->interface_params[if_id].cas_l == 0) { in hws_ddr3_tip_load_topology_map()
707 tm->interface_params[if_id].cas_l = in hws_ddr3_tip_load_topology_map()
711 if (tm->interface_params[if_id].cas_wl == 0) { in hws_ddr3_tip_load_topology_map()
712 tm->interface_params[if_id].cas_wl = in hws_ddr3_tip_load_topology_map()
726 struct hws_topology_map *tm = ddr3_get_topology_map(); in ddr3_tip_rank_control() local
729 VALIDATE_ACTIVE(tm->bus_act_mask, bus_cnt); in ddr3_tip_rank_control()
730 if ((tm->interface_params[if_id]. in ddr3_tip_rank_control()
732 tm->interface_params[if_id]. in ddr3_tip_rank_control()
734 (tm->interface_params[if_id]. in ddr3_tip_rank_control()
736 tm->interface_params[if_id]. in ddr3_tip_rank_control()
743 data_value |= tm->interface_params[if_id]. in ddr3_tip_rank_control()
745 data_value |= tm->interface_params[if_id]. in ddr3_tip_rank_control()
761 struct hws_topology_map *tm = ddr3_get_topology_map(); in ddr3_tip_pad_inv() local
764 VALIDATE_ACTIVE(tm->bus_act_mask, bus_cnt); in ddr3_tip_pad_inv()
765 if (tm->interface_params[if_id]. in ddr3_tip_pad_inv()
775 if (tm->interface_params[if_id]. in ddr3_tip_pad_inv()
940 struct hws_topology_map *tm = ddr3_get_topology_map(); in ddr3_tip_if_polling() local
952 VALIDATE_ACTIVE(tm->if_act_mask, interface_num); in ddr3_tip_if_polling()
990 struct hws_topology_map *tm = ddr3_get_topology_map(); in ddr3_tip_bus_read() local
995 VALIDATE_ACTIVE(tm->bus_act_mask, bus_index); in ddr3_tip_bus_read()
1057 struct hws_topology_map *tm = ddr3_get_topology_map(); in ddr3_tip_bus_access() local
1076 VALIDATE_ACTIVE(tm->if_act_mask, if_id); in ddr3_tip_bus_access()
1126 struct hws_topology_map *tm = ddr3_get_topology_map(); in ddr3_tip_bus_read_modify_write() local
1137 VALIDATE_ACTIVE(tm->if_act_mask, if_id); in ddr3_tip_bus_read_modify_write()
1159 struct hws_topology_map *tm = ddr3_get_topology_map(); in adll_calibration() local
1181 VALIDATE_ACTIVE(tm->bus_act_mask, bus_cnt); in adll_calibration()
1235 struct hws_topology_map *tm = ddr3_get_topology_map(); in ddr3_tip_freq_set() local
1255 VALIDATE_ACTIVE(tm->if_act_mask, if_id); in ddr3_tip_freq_set()
1268 if (IS_ACTIVE(tm->if_act_mask, if_id) == 0) in ddr3_tip_freq_set()
1273 tm->interface_params[if_id].speed_bin_index; in ddr3_tip_freq_set()
1274 if (tm->interface_params[if_id].memory_freq == in ddr3_tip_freq_set()
1277 tm->interface_params[if_id].cas_l; in ddr3_tip_freq_set()
1279 tm->interface_params[if_id].cas_wl; in ddr3_tip_freq_set()
1304 VALIDATE_ACTIVE(tm->bus_act_mask, bus_index); in ddr3_tip_freq_set()
1306 tm->interface_params[if_id]. in ddr3_tip_freq_set()
1374 t_refi = (tm->interface_params[if_id].interface_temp == in ddr3_tip_freq_set()
1433 VALIDATE_ACTIVE(tm->bus_act_mask, bus_cnt); in ddr3_tip_freq_set()
1623 struct hws_topology_map *tm = ddr3_get_topology_map(); in ddr3_tip_set_timing() local
1625 speed_bin_index = tm->interface_params[if_id].speed_bin_index; in ddr3_tip_set_timing()
1626 memory_size = tm->interface_params[if_id].memory_size; in ddr3_tip_set_timing()
1628 (tm->interface_params[if_id].bus_width == in ddr3_tip_set_timing()
1750 struct hws_topology_map *tm = ddr3_get_topology_map(); in ddr3_tip_get_first_active_if() local
1753 VALIDATE_ACTIVE(tm->if_act_mask, if_id); in ddr3_tip_get_first_active_if()
1769 struct hws_topology_map *tm = ddr3_get_topology_map(); in ddr3_tip_write_cs_result() local
1772 VALIDATE_ACTIVE(tm->if_act_mask, if_id); in ddr3_tip_write_cs_result()
1773 for (bus_num = 0; bus_num < tm->num_of_bus_per_interface; in ddr3_tip_write_cs_result()
1775 VALIDATE_ACTIVE(tm->bus_act_mask, bus_num); in ddr3_tip_write_cs_result()
1777 tm->interface_params[if_id]. in ddr3_tip_write_cs_result()
1809 struct hws_topology_map *tm = ddr3_get_topology_map(); in ddr3_tip_write_mrs_cmd() local
1815 VALIDATE_ACTIVE(tm->if_act_mask, if_id); in ddr3_tip_write_mrs_cmd()
1823 VALIDATE_ACTIVE(tm->if_act_mask, if_id); in ddr3_tip_write_mrs_cmd()
1880 struct hws_topology_map *tm = ddr3_get_topology_map(); in ddr3_tip_ddr3_reset_phy_regs() local
1883 VALIDATE_ACTIVE(tm->if_act_mask, if_id); in ddr3_tip_ddr3_reset_phy_regs()
1884 for (phy_id = 0; phy_id < tm->num_of_bus_per_interface; in ddr3_tip_ddr3_reset_phy_regs()
1886 VALIDATE_ACTIVE(tm->bus_act_mask, phy_id); in ddr3_tip_ddr3_reset_phy_regs()
1965 struct hws_topology_map *tm = ddr3_get_topology_map(); in ddr3_tip_ddr3_training_main_flow() local
1982 VALIDATE_ACTIVE(tm->if_act_mask, if_id); in ddr3_tip_ddr3_training_main_flow()
2214 freq_val[tm-> in ddr3_tip_ddr3_training_main_flow()
2219 tm->interface_params[first_active_if]. in ddr3_tip_ddr3_training_main_flow()
2264 ret = ddr3_tip_dynamic_read_leveling(dev_num, tm-> in ddr3_tip_ddr3_training_main_flow()
2435 struct hws_topology_map *tm = ddr3_get_topology_map(); in ddr3_tip_enable_init_sequence() local
2442 VALIDATE_ACTIVE(tm->if_act_mask, if_id); in ddr3_tip_enable_init_sequence()
2458 VALIDATE_ACTIVE(tm->bus_act_mask, bus_index); in ddr3_tip_enable_init_sequence()
2460 tm->interface_params[if_id]. in ddr3_tip_enable_init_sequence()
2545 struct hws_topology_map *tm = ddr3_get_topology_map(); in hws_ddr3_get_bus_width() local
2547 return (DDR3_IS_16BIT_DRAM_MODE(tm->bus_act_mask) == in hws_ddr3_get_bus_width()
2553 struct hws_topology_map *tm = ddr3_get_topology_map(); in hws_ddr3_get_device_width() local
2555 return (tm->interface_params[if_id].bus_width == in hws_ddr3_get_device_width()
2561 struct hws_topology_map *tm = ddr3_get_topology_map(); in hws_ddr3_get_device_size() local
2563 if (tm->interface_params[if_id].memory_size >= in hws_ddr3_get_device_size()
2567 tm->interface_params[if_id].memory_size)); in hws_ddr3_get_device_size()
2570 return 1 << tm->interface_params[if_id].memory_size; in hws_ddr3_get_device_size()
2618 struct hws_topology_map *tm = ddr3_get_topology_map(); in hws_ddr3_cs_base_adr_calc() local
2625 mv_hwsmem_size[tm->interface_params[0].memory_size]; in hws_ddr3_cs_base_adr_calc()