308 	enum hws_speed_bin speed_bin_index = SPEED_BIN_DDR_2133N;  in hws_ddr3_tip_init_controller()  local
353 			speed_bin_index =  in hws_ddr3_tip_init_controller()
355 				speed_bin_index;  in hws_ddr3_tip_init_controller()
364 					   memory_size, speed_bin_index, freq,  in hws_ddr3_tip_init_controller()
451 				(page_size == 1) ? speed_bin_table(speed_bin_index,  in hws_ddr3_tip_init_controller()
453 				: speed_bin_table(speed_bin_index,  in hws_ddr3_tip_init_controller()
593 					     speed_bin_table(speed_bin_index,  in hws_ddr3_tip_init_controller()
673 	enum hws_speed_bin speed_bin_index;  in hws_ddr3_tip_load_topology_map()  local
693 		speed_bin_index =  in hws_ddr3_tip_load_topology_map()
694 			tm->interface_params[if_id].speed_bin_index;  in hws_ddr3_tip_load_topology_map()
700 				   speed_bin_index, freq_val[freq],  in hws_ddr3_tip_load_topology_map()
708 				cas_latency_table[speed_bin_index].cl_val[freq];  in hws_ddr3_tip_load_topology_map()
713 				cas_write_latency_table[speed_bin_index].cl_val[freq];  in hws_ddr3_tip_load_topology_map()
1230 	enum hws_speed_bin speed_bin_index = 0;  in ddr3_tip_freq_set()  local
1272 		speed_bin_index =  in ddr3_tip_freq_set()
1273 			tm->interface_params[if_id].speed_bin_index;  in ddr3_tip_freq_set()
1282 				cas_latency_table[speed_bin_index].cl_val[frequency];  in ddr3_tip_freq_set()
1284 				cas_write_latency_table[speed_bin_index].  in ddr3_tip_freq_set()
1291 				   frequency, speed_bin_index));  in ddr3_tip_freq_set()
1296 					   cas_latency_table[speed_bin_index].  in ddr3_tip_freq_set()
1393 		t_wr = speed_bin_table(speed_bin_index, SPEED_BIN_TWR);  in ddr3_tip_freq_set()
1621 	enum hws_speed_bin speed_bin_index;  in ddr3_tip_set_timing()  local
1625 	speed_bin_index = tm->interface_params[if_id].speed_bin_index;  in ddr3_tip_set_timing()
1632 	t_rrd =	(page_size == 1) ? speed_bin_table(speed_bin_index,  in ddr3_tip_set_timing()
1634 		speed_bin_table(speed_bin_index, SPEED_BIN_TRRD2K);  in ddr3_tip_set_timing()
1636 	t_rtp =	GET_MAX_VALUE(t_ckclk * 4, speed_bin_table(speed_bin_index,  in ddr3_tip_set_timing()
1638 	t_wtr = GET_MAX_VALUE(t_ckclk * 4, speed_bin_table(speed_bin_index,  in ddr3_tip_set_timing()
1640 	t_ras = TIME_2_CLOCK_CYCLES(speed_bin_table(speed_bin_index,  in ddr3_tip_set_timing()
1643 	t_rcd = TIME_2_CLOCK_CYCLES(speed_bin_table(speed_bin_index,  in ddr3_tip_set_timing()
1646 	t_rp = TIME_2_CLOCK_CYCLES(speed_bin_table(speed_bin_index,  in ddr3_tip_set_timing()
1649 	t_wr = TIME_2_CLOCK_CYCLES(speed_bin_table(speed_bin_index,  in ddr3_tip_set_timing()