72 u32 mask_tune_func = (SET_MEDIUM_FREQ_MASK_BIT |  variable
2000 	if (mask_tune_func & INIT_CONTROLLER_MASK_BIT) {  in ddr3_tip_ddr3_training_main_flow()
2020 	if (mask_tune_func & STATIC_LEVELING_MASK_BIT) {  in ddr3_tip_ddr3_training_main_flow()
2036 	if (mask_tune_func & SET_LOW_FREQ_MASK_BIT) {  in ddr3_tip_ddr3_training_main_flow()
2054 		if (mask_tune_func & LOAD_PATTERN_MASK_BIT) {  in ddr3_tip_ddr3_training_main_flow()
2074 	if (mask_tune_func & SET_MEDIUM_FREQ_MASK_BIT) {  in ddr3_tip_ddr3_training_main_flow()
2092 	if (mask_tune_func & WRITE_LEVELING_MASK_BIT) {  in ddr3_tip_ddr3_training_main_flow()
2114 		if (mask_tune_func & LOAD_PATTERN_2_MASK_BIT) {  in ddr3_tip_ddr3_training_main_flow()
2134 	if (mask_tune_func & READ_LEVELING_MASK_BIT) {  in ddr3_tip_ddr3_training_main_flow()
2155 	if (mask_tune_func & WRITE_LEVELING_SUPP_MASK_BIT) {  in ddr3_tip_ddr3_training_main_flow()
2171 		if (mask_tune_func & PBS_RX_MASK_BIT) {  in ddr3_tip_ddr3_training_main_flow()
2190 		if (mask_tune_func & PBS_TX_MASK_BIT) {  in ddr3_tip_ddr3_training_main_flow()
2210 	if (mask_tune_func & SET_TARGET_FREQ_MASK_BIT) {  in ddr3_tip_ddr3_training_main_flow()
2231 	if (mask_tune_func & WRITE_LEVELING_TF_MASK_BIT) {  in ddr3_tip_ddr3_training_main_flow()
2246 	if (mask_tune_func & LOAD_PATTERN_HIGH_MASK_BIT) {  in ddr3_tip_ddr3_training_main_flow()
2260 	if (mask_tune_func & READ_LEVELING_TF_MASK_BIT) {  in ddr3_tip_ddr3_training_main_flow()
2277 	if (mask_tune_func & DM_PBS_TX_MASK_BIT) {  in ddr3_tip_ddr3_training_main_flow()
2282 		if (mask_tune_func & VREF_CALIBRATION_MASK_BIT) {  in ddr3_tip_ddr3_training_main_flow()
2303 		if (mask_tune_func & CENTRALIZATION_RX_MASK_BIT) {  in ddr3_tip_ddr3_training_main_flow()
2324 		if (mask_tune_func & WRITE_LEVELING_SUPP_TF_MASK_BIT) {  in ddr3_tip_ddr3_training_main_flow()
2345 		if (mask_tune_func & CENTRALIZATION_TX_MASK_BIT) {  in ddr3_tip_ddr3_training_main_flow()