Lines Matching refs:interface_params
214 data = (tm->interface_params[if_id].bus_width == in ddr3_tip_configure_cs()
220 mem_index = tm->interface_params[if_id].memory_size; in ddr3_tip_configure_cs()
275 cs_bitmask = tm->interface_params[if_id]. in calc_cs_num()
339 tm->interface_params[if_id]. in hws_ddr3_tip_init_controller()
351 tm->interface_params[if_id]. in hws_ddr3_tip_init_controller()
354 tm->interface_params[if_id]. in hws_ddr3_tip_init_controller()
358 (tm->interface_params[if_id]. in hws_ddr3_tip_init_controller()
444 (tm->interface_params[if_id]. in hws_ddr3_tip_init_controller()
464 (tm->interface_params[if_id]. in hws_ddr3_tip_init_controller()
473 tm->interface_params[if_id]. in hws_ddr3_tip_init_controller()
502 tm->interface_params[if_id]. in hws_ddr3_tip_init_controller()
505 tm->interface_params[if_id]. in hws_ddr3_tip_init_controller()
540 ((tm->interface_params[if_id]. in hws_ddr3_tip_init_controller()
573 timing = tm->interface_params[if_id].timing; in hws_ddr3_tip_init_controller()
694 tm->interface_params[if_id].speed_bin_index; in hws_ddr3_tip_load_topology_map()
696 freq = tm->interface_params[first_active_if].memory_freq; in hws_ddr3_tip_load_topology_map()
701 tm->interface_params[if_id]. in hws_ddr3_tip_load_topology_map()
703 tm->interface_params[if_id]. in hws_ddr3_tip_load_topology_map()
706 if (tm->interface_params[if_id].cas_l == 0) { in hws_ddr3_tip_load_topology_map()
707 tm->interface_params[if_id].cas_l = in hws_ddr3_tip_load_topology_map()
711 if (tm->interface_params[if_id].cas_wl == 0) { in hws_ddr3_tip_load_topology_map()
712 tm->interface_params[if_id].cas_wl = in hws_ddr3_tip_load_topology_map()
730 if ((tm->interface_params[if_id]. in ddr3_tip_rank_control()
732 tm->interface_params[if_id]. in ddr3_tip_rank_control()
734 (tm->interface_params[if_id]. in ddr3_tip_rank_control()
736 tm->interface_params[if_id]. in ddr3_tip_rank_control()
743 data_value |= tm->interface_params[if_id]. in ddr3_tip_rank_control()
745 data_value |= tm->interface_params[if_id]. in ddr3_tip_rank_control()
765 if (tm->interface_params[if_id]. in ddr3_tip_pad_inv()
775 if (tm->interface_params[if_id]. in ddr3_tip_pad_inv()
1273 tm->interface_params[if_id].speed_bin_index; in ddr3_tip_freq_set()
1274 if (tm->interface_params[if_id].memory_freq == in ddr3_tip_freq_set()
1277 tm->interface_params[if_id].cas_l; in ddr3_tip_freq_set()
1279 tm->interface_params[if_id].cas_wl; in ddr3_tip_freq_set()
1306 tm->interface_params[if_id]. in ddr3_tip_freq_set()
1374 t_refi = (tm->interface_params[if_id].interface_temp == in ddr3_tip_freq_set()
1625 speed_bin_index = tm->interface_params[if_id].speed_bin_index; in ddr3_tip_set_timing()
1626 memory_size = tm->interface_params[if_id].memory_size; in ddr3_tip_set_timing()
1628 (tm->interface_params[if_id].bus_width == in ddr3_tip_set_timing()
1777 tm->interface_params[if_id]. in ddr3_tip_write_cs_result()
2215 interface_params[first_active_if]. in ddr3_tip_ddr3_training_main_flow()
2219 tm->interface_params[first_active_if]. in ddr3_tip_ddr3_training_main_flow()
2265 interface_params[first_active_if]. in ddr3_tip_ddr3_training_main_flow()
2460 tm->interface_params[if_id]. in ddr3_tip_enable_init_sequence()
2555 return (tm->interface_params[if_id].bus_width == in hws_ddr3_get_device_width()
2563 if (tm->interface_params[if_id].memory_size >= in hws_ddr3_get_device_size()
2567 tm->interface_params[if_id].memory_size)); in hws_ddr3_get_device_size()
2570 return 1 << tm->interface_params[if_id].memory_size; in hws_ddr3_get_device_size()
2625 mv_hwsmem_size[tm->interface_params[0].memory_size]; in hws_ddr3_cs_base_adr_calc()