Lines Matching refs:init_cntr_prm
300 int hws_ddr3_tip_init_controller(u32 dev_num, struct init_cntr_param *init_cntr_prm) in hws_ddr3_tip_init_controller() argument
321 init_cntr_prm->do_mrs_phy, in hws_ddr3_tip_init_controller()
322 init_cntr_prm->is_ctrl64_bit)); in hws_ddr3_tip_init_controller()
324 if (init_cntr_prm->init_phy == 1) { in hws_ddr3_tip_init_controller()
376 if (init_cntr_prm->is_ctrl64_bit) in hws_ddr3_tip_init_controller()
405 if (init_cntr_prm->is_ctrl64_bit) { in hws_ddr3_tip_init_controller()
491 if (init_cntr_prm->do_mrs_phy) { in hws_ddr3_tip_init_controller()
559 if (init_cntr_prm->is_ctrl64_bit) { in hws_ddr3_tip_init_controller()
571 (init_cntr_prm->msys_init << 7), (1 << 7))); in hws_ddr3_tip_init_controller()
644 if (init_cntr_prm->do_mrs_phy) { in hws_ddr3_tip_init_controller()
1961 struct init_cntr_param init_cntr_prm; in ddr3_tip_ddr3_training_main_flow() local
2004 init_cntr_prm.do_mrs_phy = 1; in ddr3_tip_ddr3_training_main_flow()
2005 init_cntr_prm.is_ctrl64_bit = 0; in ddr3_tip_ddr3_training_main_flow()
2006 init_cntr_prm.init_phy = 1; in ddr3_tip_ddr3_training_main_flow()
2007 init_cntr_prm.msys_init = 0; in ddr3_tip_ddr3_training_main_flow()
2008 ret = hws_ddr3_tip_init_controller(dev_num, &init_cntr_prm); in ddr3_tip_ddr3_training_main_flow()