Lines Matching refs:MV_OK
201 return MV_OK; in ddr3_tip_tune_training_params()
257 return MV_OK; in ddr3_tip_configure_cs()
294 return MV_OK; in calc_cs_num()
665 return MV_OK; in hws_ddr3_tip_init_controller()
717 return MV_OK; in hws_ddr3_tip_load_topology_map()
752 return MV_OK; in ddr3_tip_rank_control()
793 return MV_OK; in ddr3_tip_pad_inv()
801 int ret = MV_OK, ret_tune = MV_OK; in hws_ddr3_tip_run_alg()
832 if (ret != MV_OK) { in hws_ddr3_tip_run_alg()
846 int ret = MV_OK, ret_tune = MV_OK; in odt_test()
874 if (ret_tune != MV_OK) { in odt_test()
877 ret = (ret == MV_OK) ? ret_tune : ret; in odt_test()
960 if (ret != MV_OK) in ddr3_tip_if_polling()
978 return (is_fail == 0) ? MV_OK : MV_FAIL; in ddr3_tip_if_polling()
1023 return MV_OK; in ddr3_tip_bus_read()
1038 return MV_OK; in ddr3_tip_bus_write()
1081 return MV_OK; in ddr3_tip_bus_access()
1112 return MV_OK; in is_bus_access_done()
1148 return MV_OK; in ddr3_tip_bus_read_modify_write()
1204 MAX_POLLING_ITERATIONS) != MV_OK) { in adll_calibration()
1218 return MV_OK; in adll_calibration()
1359 MAX_POLLING_ITERATIONS) != MV_OK) { in ddr3_tip_freq_set()
1463 MAX_POLLING_ITERATIONS) != MV_OK) { in ddr3_tip_freq_set()
1490 MAX_POLLING_ITERATIONS) != MV_OK) { in ddr3_tip_freq_set()
1501 SDRAM_OPERATION_REG, MAX_POLLING_ITERATIONS) != MV_OK) { in ddr3_tip_freq_set()
1575 return MV_OK; in ddr3_tip_freq_set()
1608 return MV_OK; in ddr3_tip_write_odt()
1698 return MV_OK; in ddr3_tip_set_timing()
1710 if (ret != MV_OK) in hws_ddr3_tip_mode_read()
1715 if (ret != MV_OK) in hws_ddr3_tip_mode_read()
1720 if (ret != MV_OK) in hws_ddr3_tip_mode_read()
1725 if (ret != MV_OK) in hws_ddr3_tip_mode_read()
1731 if (ret != MV_OK) in hws_ddr3_tip_mode_read()
1737 if (ret != MV_OK) in hws_ddr3_tip_mode_read()
1740 return MV_OK; in hws_ddr3_tip_mode_read()
1760 return MV_OK; in ddr3_tip_get_first_active_if()
1799 return MV_OK; in ddr3_tip_write_cs_result()
1826 MAX_POLLING_ITERATIONS) != MV_OK) { in ddr3_tip_write_mrs_cmd()
1832 return MV_OK; in ddr3_tip_write_mrs_cmd()
1871 return MV_OK; in ddr3_tip_reset_fifo_ptr()
1921 return MV_OK; in ddr3_tip_ddr3_reset_phy_regs()
1952 return MV_OK; in ddr3_tip_restore_dunit_regs()
1962 int ret = MV_OK; in ddr3_tip_ddr3_training_main_flow()
2011 if (ret != MV_OK) { in ddr3_tip_ddr3_training_main_flow()
2027 if (ret != MV_OK) { in ddr3_tip_ddr3_training_main_flow()
2045 if (ret != MV_OK) { in ddr3_tip_ddr3_training_main_flow()
2062 if (ret != MV_OK) { in ddr3_tip_ddr3_training_main_flow()
2084 if (ret != MV_OK) { in ddr3_tip_ddr3_training_main_flow()
2105 if (ret != MV_OK) { in ddr3_tip_ddr3_training_main_flow()
2122 if (ret != MV_OK) { in ddr3_tip_ddr3_training_main_flow()
2147 if (ret != MV_OK) { in ddr3_tip_ddr3_training_main_flow()
2162 if (ret != MV_OK) { in ddr3_tip_ddr3_training_main_flow()
2179 if (ret != MV_OK) { in ddr3_tip_ddr3_training_main_flow()
2198 if (ret != MV_OK) { in ddr3_tip_ddr3_training_main_flow()
2223 if (ret != MV_OK) { in ddr3_tip_ddr3_training_main_flow()
2238 if (ret != MV_OK) { in ddr3_tip_ddr3_training_main_flow()
2252 if (ret != MV_OK) { in ddr3_tip_ddr3_training_main_flow()
2269 if (ret != MV_OK) { in ddr3_tip_ddr3_training_main_flow()
2291 if (ret != MV_OK) { in ddr3_tip_ddr3_training_main_flow()
2311 if (ret != MV_OK) { in ddr3_tip_ddr3_training_main_flow()
2332 if (ret != MV_OK) { in ddr3_tip_ddr3_training_main_flow()
2353 if (ret != MV_OK) { in ddr3_tip_ddr3_training_main_flow()
2372 return MV_OK; in ddr3_tip_ddr3_training_main_flow()
2404 if (ret != MV_OK) { in ddr3_tip_ddr3_auto_tune()
2425 return MV_OK; in ddr3_tip_ddr3_auto_tune()
2447 MAX_POLLING_ITERATIONS) != MV_OK) { in ddr3_tip_enable_init_sequence()
2473 return (is_fail == 0) ? MV_OK : MV_FAIL; in ddr3_tip_enable_init_sequence()
2480 return MV_OK; in ddr3_tip_register_dq_table()
2600 return MV_OK; in hws_ddr3_calc_mem_cs_size()
2614 if (hws_ddr3_calc_mem_cs_size(if_id, cs, &cs_mem_size) != MV_OK) in hws_ddr3_cs_base_adr_calc()
2649 return MV_OK; in hws_ddr3_cs_base_adr_calc()