49 enum hws_result training_result[MAX_STAGE_LIMIT][MAX_INTERFACE_NUM];
316 	u32 data_read[MAX_INTERFACE_NUM];  in hws_ddr3_tip_init_controller()
329 		for (if_id = 0; if_id <= MAX_INTERFACE_NUM - 1; if_id++) {  in hws_ddr3_tip_init_controller()
640 	for (if_id = 0; if_id <= MAX_INTERFACE_NUM - 1; if_id++) {  in hws_ddr3_tip_init_controller()
691 	for (if_id = 0; if_id <= MAX_INTERFACE_NUM - 1; if_id++) {  in hws_ddr3_tip_load_topology_map()
937 	u32 read_data[MAX_INTERFACE_NUM];  in ddr3_tip_if_polling()
944 		end_if = MAX_INTERFACE_NUM - 1;  in ddr3_tip_if_polling()
989 	u32 data_read[MAX_INTERFACE_NUM];  in ddr3_tip_bus_read()
1071 		end_if = MAX_INTERFACE_NUM - 1;  in ddr3_tip_bus_access()
1092 	u32 data_read[MAX_INTERFACE_NUM];  in is_bus_access_done()
1130 		end_if = MAX_INTERFACE_NUM - 1;  in ddr3_tip_bus_read_modify_write()
1234 	u32 cs_mask[MAX_INTERFACE_NUM];  in ddr3_tip_freq_set()
1245 		end_if = MAX_INTERFACE_NUM - 1;  in ddr3_tip_freq_set()
1253 	for (if_id = 0; if_id <= MAX_INTERFACE_NUM - 1; if_id++) {  in ddr3_tip_freq_set()
1752 	for (if_id = 0; if_id <= MAX_INTERFACE_NUM - 1; if_id++) {  in ddr3_tip_get_first_active_if()
1771 	for (if_id = 0; if_id <= MAX_INTERFACE_NUM - 1; if_id++) {  in ddr3_tip_write_cs_result()
1814 	for (if_id = 0; if_id <= MAX_INTERFACE_NUM - 1; if_id++) {  in ddr3_tip_write_mrs_cmd()
1822 	for (if_id = 0; if_id <= MAX_INTERFACE_NUM - 1; if_id++) {  in ddr3_tip_write_mrs_cmd()
1882 	for (if_id = 0; if_id <= MAX_INTERFACE_NUM - 1; if_id++) {  in ddr3_tip_ddr3_reset_phy_regs()
1981 		for (if_id = 0; if_id < MAX_INTERFACE_NUM; if_id++) {  in ddr3_tip_ddr3_training_main_flow()
2385 	for (if_id = 0; if_id <= MAX_INTERFACE_NUM - 1; if_id++) {  in ddr3_tip_ddr3_auto_tune()
2408 	for (if_id = 0; if_id <= MAX_INTERFACE_NUM - 1; if_id++) {  in ddr3_tip_ddr3_auto_tune()
2441 	for (if_id = 0; if_id <= MAX_INTERFACE_NUM - 1; if_id++) {  in ddr3_tip_enable_init_sequence()