Lines Matching refs:mask_tune_func
358 if (mask_tune_func & INIT_CONTROLLER_MASK_BIT) { in ddr3_tip_print_log()
365 if (mask_tune_func & SET_LOW_FREQ_MASK_BIT) { in ddr3_tip_print_log()
372 if (mask_tune_func & LOAD_PATTERN_MASK_BIT) { in ddr3_tip_print_log()
379 if (mask_tune_func & SET_MEDIUM_FREQ_MASK_BIT) { in ddr3_tip_print_log()
386 if (mask_tune_func & WRITE_LEVELING_MASK_BIT) { in ddr3_tip_print_log()
393 if (mask_tune_func & LOAD_PATTERN_2_MASK_BIT) { in ddr3_tip_print_log()
400 if (mask_tune_func & READ_LEVELING_MASK_BIT) { in ddr3_tip_print_log()
407 if (mask_tune_func & WRITE_LEVELING_SUPP_MASK_BIT) { in ddr3_tip_print_log()
414 if (mask_tune_func & PBS_RX_MASK_BIT) { in ddr3_tip_print_log()
421 if (mask_tune_func & PBS_TX_MASK_BIT) { in ddr3_tip_print_log()
428 if (mask_tune_func & SET_TARGET_FREQ_MASK_BIT) { in ddr3_tip_print_log()
435 if (mask_tune_func & WRITE_LEVELING_TF_MASK_BIT) { in ddr3_tip_print_log()
442 if (mask_tune_func & READ_LEVELING_TF_MASK_BIT) { in ddr3_tip_print_log()
449 if (mask_tune_func & WRITE_LEVELING_SUPP_TF_MASK_BIT) { in ddr3_tip_print_log()
457 if (mask_tune_func & CENTRALIZATION_RX_MASK_BIT) { in ddr3_tip_print_log()
464 if (mask_tune_func & VREF_CALIBRATION_MASK_BIT) { in ddr3_tip_print_log()
471 if (mask_tune_func & CENTRALIZATION_TX_MASK_BIT) { in ddr3_tip_print_log()
829 *ptr = (u32 *)&mask_tune_func; in ddr3_tip_access_atr()