Lines Matching refs:dev_num
198 static int ddr3_tip_a38x_set_divider(u8 dev_num, u32 if_id,
204 u32 ddr3_ctrl_get_junc_temp(u8 dev_num) in ddr3_ctrl_get_junc_temp() argument
232 int ddr3_tip_a38x_get_freq_config(u8 dev_num, enum hws_ddr_freq freq, in ddr3_tip_a38x_get_freq_config() argument
256 int ddr3_tip_a38x_pipe_enable(u8 dev_num, enum hws_access_type interface_access, in ddr3_tip_a38x_pipe_enable() argument
271 (dev_num, PIPE_ENABLE_ADDR, &data_value, MASK_ALL_BITS)); in ddr3_tip_a38x_pipe_enable()
273 CHECK_STATUS(ddr3_tip_reg_write(dev_num, PIPE_ENABLE_ADDR, data_value)); in ddr3_tip_a38x_pipe_enable()
285 int ddr3_tip_a38x_if_write(u8 dev_num, enum hws_access_type interface_access, in ddr3_tip_a38x_if_write() argument
293 (dev_num, ACCESS_TYPE_UNICAST, if_id, reg_addr, in ddr3_tip_a38x_if_write()
310 int ddr3_tip_a38x_if_read(u8 dev_num, enum hws_access_type interface_access, in ddr3_tip_a38x_if_read() argument
326 int ddr3_tip_a38x_select_ddr_controller(u8 dev_num, int enable) in ddr3_tip_a38x_select_ddr_controller() argument
349 static int ddr3_tip_init_a38x_silicon(u32 dev_num, u32 board_id) in ddr3_tip_init_a38x_silicon() argument
367 ddr3_tip_init_config_func(dev_num, &config_func); in ddr3_tip_init_a38x_silicon()
369 ddr3_tip_register_dq_table(dev_num, dq_bit_map_2_phy_pin); in ddr3_tip_init_a38x_silicon()
384 ddr3_tip_init_static_config_db(dev_num, &static_config); in ddr3_tip_init_a38x_silicon()
387 status = ddr3_tip_a38x_get_init_freq(dev_num, &ddr_freq); in ddr3_tip_init_a38x_silicon()
443 ddr3_tip_a38x_get_medium_freq(dev_num, &medium_freq); in ddr3_tip_init_a38x_silicon()
448 int ddr3_a38x_update_topology_map(u32 dev_num, struct hws_topology_map *tm) in ddr3_a38x_update_topology_map() argument
453 ddr3_tip_a38x_get_init_freq(dev_num, &freq); in ddr3_a38x_update_topology_map()
460 CHECK_STATUS(hws_ddr3_tip_load_topology_map(dev_num, tm)); in ddr3_a38x_update_topology_map()
465 int ddr3_tip_init_a38x(u32 dev_num, u32 board_id) in ddr3_tip_init_a38x() argument
472 ddr3_a38x_update_topology_map(dev_num, tm); in ddr3_tip_init_a38x()
473 ddr3_tip_init_a38x_silicon(dev_num, board_id); in ddr3_tip_init_a38x()
478 int ddr3_tip_a38x_get_init_freq(int dev_num, enum hws_ddr_freq *freq) in ddr3_tip_a38x_get_init_freq() argument
529 int ddr3_tip_a38x_get_medium_freq(int dev_num, enum hws_ddr_freq *freq) in ddr3_tip_a38x_get_medium_freq() argument
588 static int ddr3_tip_a38x_set_divider(u8 dev_num, u32 if_id, in ddr3_tip_a38x_set_divider() argument
609 (dev_num, ACCESS_TYPE_UNICAST, if_id, 0x20220, 0x0, in ddr3_tip_a38x_set_divider()
612 (dev_num, ACCESS_TYPE_UNICAST, if_id, 0xe42f4, 0x0, in ddr3_tip_a38x_set_divider()
617 (dev_num, ACCESS_TYPE_UNICAST, if_id, 0xe4264, 0x1f, in ddr3_tip_a38x_set_divider()
622 (dev_num, ACCESS_TYPE_UNICAST, if_id, 0xe4260, in ddr3_tip_a38x_set_divider()
627 (dev_num, ACCESS_TYPE_UNICAST, if_id, 0xe4260, in ddr3_tip_a38x_set_divider()
632 (dev_num, ACCESS_TYPE_UNICAST, if_id, 0xe4268, in ddr3_tip_a38x_set_divider()
637 (dev_num, ACCESS_TYPE_UNICAST, if_id, 0xe4264, in ddr3_tip_a38x_set_divider()
642 (dev_num, ACCESS_TYPE_UNICAST, if_id, 0xe4264, 0, in ddr3_tip_a38x_set_divider()
647 (dev_num, ACCESS_TYPE_UNICAST, if_id, 0xe4260, 0, in ddr3_tip_a38x_set_divider()
652 (dev_num, ACCESS_TYPE_UNICAST, if_id, 0xe4260, 0, in ddr3_tip_a38x_set_divider()
657 (dev_num, ACCESS_TYPE_UNICAST, if_id, 0xe4264, 0, in ddr3_tip_a38x_set_divider()
663 (dev_num, ACCESS_TYPE_UNICAST, if_id, 0x18488, in ddr3_tip_a38x_set_divider()
666 (dev_num, ACCESS_TYPE_UNICAST, if_id, 0x1524, in ddr3_tip_a38x_set_divider()
670 (dev_num, ACCESS_TYPE_UNICAST, if_id, 0x18488, in ddr3_tip_a38x_set_divider()
673 (dev_num, ACCESS_TYPE_UNICAST, if_id, 0x1524, in ddr3_tip_a38x_set_divider()
683 int ddr3_tip_ext_read(u32 dev_num, u32 if_id, u32 reg_addr, in ddr3_tip_ext_read() argument
697 int ddr3_tip_ext_write(u32 dev_num, u32 if_id, u32 reg_addr, in ddr3_tip_ext_write() argument
731 int ddr3_tip_a38x_get_device_info(u8 dev_num, struct ddr3_device_info *info_ptr) in ddr3_tip_a38x_get_device_info() argument