Lines Matching refs:setbits_be32

350 		setbits_be32(&ddr->debug[0], 1);  in fsl_ddr_set_memctl_regs()
361 	setbits_be32(&ecm->eebacr, 0x10000000);  in fsl_ddr_set_memctl_regs()
365 	setbits_be32(&ddr->sdram_cfg_2, SDRAM_CFG2_D_INIT);  in fsl_ddr_set_memctl_regs()
370 	setbits_be32(&ddr->debug[2], 0x400);  in fsl_ddr_set_memctl_regs()
387 		setbits_be32(&ddr->sdram_cfg_2, SDRAM_CFG2_FRC_SR);  in fsl_ddr_set_memctl_regs()
456 	setbits_be32(&ddr->debug[0], 0x10000);  in fsl_ddr_set_memctl_regs()
460 	setbits_be32(&ddr->timing_cfg_2, TIMING_CFG_2_CPO_MASK);  in fsl_ddr_set_memctl_regs()
473 	setbits_be32(&ddr->debug[1], 0x800);  in fsl_ddr_set_memctl_regs()
485 	setbits_be32(&ddr->sdram_cfg_2,  in fsl_ddr_set_memctl_regs()
491 	setbits_be32(&ddr->debug[1], 0x400);  in fsl_ddr_set_memctl_regs()
503 	setbits_be32(&ddr->sdram_cfg_2,  in fsl_ddr_set_memctl_regs()
528 		setbits_be32(&ddr->sdram_cfg, 0x2);	/* MEM_HALT */  in fsl_ddr_set_memctl_regs()