Lines Matching refs:sdram_cfg_2
153 out_be32(&ddr->sdram_cfg_2, in fsl_ddr_set_memctl_regs()
164 out_be32(&ddr->sdram_cfg_2, regs->ddr_sdram_cfg_2); in fsl_ddr_set_memctl_regs()
208 out_be32(&ddr->sdram_cfg_2, regs->ddr_sdram_cfg_2 & 0xffffffeb); in fsl_ddr_set_memctl_regs()
333 out_be32(&ddr->sdram_cfg_2, regs->ddr_sdram_cfg_2); in fsl_ddr_set_memctl_regs()
365 setbits_be32(&ddr->sdram_cfg_2, SDRAM_CFG2_D_INIT); in fsl_ddr_set_memctl_regs()
367 in_be32(&ddr->sdram_cfg_2)); in fsl_ddr_set_memctl_regs()
387 setbits_be32(&ddr->sdram_cfg_2, SDRAM_CFG2_FRC_SR); in fsl_ddr_set_memctl_regs()
433 while ((in_be32(&ddr->sdram_cfg_2) & SDRAM_CFG2_D_INIT) && in fsl_ddr_set_memctl_regs()
451 clrbits_be32(&ddr->sdram_cfg_2, SDRAM_CFG2_ODT_CFG_MASK); in fsl_ddr_set_memctl_regs()
453 in_be32(&ddr->sdram_cfg_2)); in fsl_ddr_set_memctl_regs()
485 setbits_be32(&ddr->sdram_cfg_2, in fsl_ddr_set_memctl_regs()
487 debug("Setting sdram_cfg_2 to 0x%08x\n", in_be32(&ddr->sdram_cfg_2)); in fsl_ddr_set_memctl_regs()
503 setbits_be32(&ddr->sdram_cfg_2, in fsl_ddr_set_memctl_regs()
505 debug("Setting sdram_cfg_2 to 0x%08x\n", in_be32(&ddr->sdram_cfg_2)); in fsl_ddr_set_memctl_regs()
510 while ((in_be32(&ddr->sdram_cfg_2) & SDRAM_CFG2_D_INIT) && in fsl_ddr_set_memctl_regs()
551 clrbits_be32(&ddr->sdram_cfg_2, SDRAM_CFG2_FRC_SR); in fsl_ddr_set_memctl_regs()