Lines Matching refs:sdram_cfg

200 	out_be32(&ddr->sdram_cfg, temp_sdram_cfg);  in fsl_ddr_set_memctl_regs()
215 		out_be32(&ddr->sdram_cfg, temp_sdram_cfg | SDRAM_CFG_BI | SDRAM_CFG_MEM_EN);  in fsl_ddr_set_memctl_regs()
328 		out_be32(&ddr->sdram_cfg, temp_sdram_cfg);  in fsl_ddr_set_memctl_regs()
347 	if ((((in_be32(&ddr->sdram_cfg) >> 24) & 0x7) == SDRAM_TYPE_DDR2)  in fsl_ddr_set_memctl_regs()
348 	    && in_be32(&ddr->sdram_cfg) & 0x80000) {  in fsl_ddr_set_memctl_regs()
390 		temp_sdram_cfg = (in_be32(&ddr->sdram_cfg) | SDRAM_CFG_BI);  in fsl_ddr_set_memctl_regs()
393 		temp_sdram_cfg = (in_be32(&ddr->sdram_cfg) & ~SDRAM_CFG_BI);  in fsl_ddr_set_memctl_regs()
396 	out_be32(&ddr->sdram_cfg, temp_sdram_cfg | SDRAM_CFG_MEM_EN);  in fsl_ddr_set_memctl_regs()
421 	bus_width = 3 - ((ddr->sdram_cfg & SDRAM_CFG_DBW_MASK)  in fsl_ddr_set_memctl_regs()
528 		setbits_be32(&ddr->sdram_cfg, 0x2);	/* MEM_HALT */  in fsl_ddr_set_memctl_regs()
545 		clrbits_be32(&ddr->sdram_cfg, 0x2);  in fsl_ddr_set_memctl_regs()