25 void fsl_ddr_set_memctl_regs(const fsl_ddr_cfg_regs_t *regs,  in fsl_ddr_set_memctl_regs()  argument
70 	if (regs->ddr_eor)  in fsl_ddr_set_memctl_regs()
71 		out_be32(&ddr->eor, regs->ddr_eor);  in fsl_ddr_set_memctl_regs()
75 		cs_sa = (regs->cs[i].bnds >> 16) & 0xfff;  in fsl_ddr_set_memctl_regs()
76 		cs_ea = regs->cs[i].bnds & 0xfff;  in fsl_ddr_set_memctl_regs()
79 			csn_bnds_backup = regs->cs[i].bnds;  in fsl_ddr_set_memctl_regs()
80 			csn_bnds_t = (unsigned int *) &regs->cs[i].bnds;  in fsl_ddr_set_memctl_regs()
82 				*csn_bnds_t = regs->cs[i].bnds + 0x01000000;  in fsl_ddr_set_memctl_regs()
84 				*csn_bnds_t = regs->cs[i].bnds + 0x01000100;  in fsl_ddr_set_memctl_regs()
87 				csn, csn_bnds_backup, regs->cs[i].bnds);  in fsl_ddr_set_memctl_regs()
94 			out_be32(&ddr->cs0_bnds, regs->cs[i].bnds);  in fsl_ddr_set_memctl_regs()
95 			out_be32(&ddr->cs0_config, regs->cs[i].config);  in fsl_ddr_set_memctl_regs()
96 			out_be32(&ddr->cs0_config_2, regs->cs[i].config_2);  in fsl_ddr_set_memctl_regs()
99 			out_be32(&ddr->cs1_bnds, regs->cs[i].bnds);  in fsl_ddr_set_memctl_regs()
100 			out_be32(&ddr->cs1_config, regs->cs[i].config);  in fsl_ddr_set_memctl_regs()
101 			out_be32(&ddr->cs1_config_2, regs->cs[i].config_2);  in fsl_ddr_set_memctl_regs()
104 			out_be32(&ddr->cs2_bnds, regs->cs[i].bnds);  in fsl_ddr_set_memctl_regs()
105 			out_be32(&ddr->cs2_config, regs->cs[i].config);  in fsl_ddr_set_memctl_regs()
106 			out_be32(&ddr->cs2_config_2, regs->cs[i].config_2);  in fsl_ddr_set_memctl_regs()
109 			out_be32(&ddr->cs3_bnds, regs->cs[i].bnds);  in fsl_ddr_set_memctl_regs()
110 			out_be32(&ddr->cs3_config, regs->cs[i].config);  in fsl_ddr_set_memctl_regs()
111 			out_be32(&ddr->cs3_config_2, regs->cs[i].config_2);  in fsl_ddr_set_memctl_regs()
115 	out_be32(&ddr->timing_cfg_3, regs->timing_cfg_3);  in fsl_ddr_set_memctl_regs()
116 	out_be32(&ddr->timing_cfg_0, regs->timing_cfg_0);  in fsl_ddr_set_memctl_regs()
117 	out_be32(&ddr->timing_cfg_1, regs->timing_cfg_1);  in fsl_ddr_set_memctl_regs()
118 	out_be32(&ddr->timing_cfg_2, regs->timing_cfg_2);  in fsl_ddr_set_memctl_regs()
119 	out_be32(&ddr->sdram_mode, regs->ddr_sdram_mode);  in fsl_ddr_set_memctl_regs()
120 	out_be32(&ddr->sdram_mode_2, regs->ddr_sdram_mode_2);  in fsl_ddr_set_memctl_regs()
121 	out_be32(&ddr->sdram_mode_3, regs->ddr_sdram_mode_3);  in fsl_ddr_set_memctl_regs()
122 	out_be32(&ddr->sdram_mode_4, regs->ddr_sdram_mode_4);  in fsl_ddr_set_memctl_regs()
123 	out_be32(&ddr->sdram_mode_5, regs->ddr_sdram_mode_5);  in fsl_ddr_set_memctl_regs()
124 	out_be32(&ddr->sdram_mode_6, regs->ddr_sdram_mode_6);  in fsl_ddr_set_memctl_regs()
125 	out_be32(&ddr->sdram_mode_7, regs->ddr_sdram_mode_7);  in fsl_ddr_set_memctl_regs()
126 	out_be32(&ddr->sdram_mode_8, regs->ddr_sdram_mode_8);  in fsl_ddr_set_memctl_regs()
127 	out_be32(&ddr->sdram_md_cntl, regs->ddr_sdram_md_cntl);  in fsl_ddr_set_memctl_regs()
128 	out_be32(&ddr->sdram_interval, regs->ddr_sdram_interval);  in fsl_ddr_set_memctl_regs()
129 	out_be32(&ddr->sdram_data_init, regs->ddr_data_init);  in fsl_ddr_set_memctl_regs()
130 	out_be32(&ddr->sdram_clk_cntl, regs->ddr_sdram_clk_cntl);  in fsl_ddr_set_memctl_regs()
131 	out_be32(&ddr->timing_cfg_4, regs->timing_cfg_4);  in fsl_ddr_set_memctl_regs()
132 	out_be32(&ddr->timing_cfg_5, regs->timing_cfg_5);  in fsl_ddr_set_memctl_regs()
133 	out_be32(&ddr->ddr_zq_cntl, regs->ddr_zq_cntl);  in fsl_ddr_set_memctl_regs()
134 	out_be32(&ddr->ddr_wrlvl_cntl, regs->ddr_wrlvl_cntl);  in fsl_ddr_set_memctl_regs()
141 	if (regs->ddr_wrlvl_cntl_2)  in fsl_ddr_set_memctl_regs()
142 		out_be32(&ddr->ddr_wrlvl_cntl_2, regs->ddr_wrlvl_cntl_2);  in fsl_ddr_set_memctl_regs()
143 	if (regs->ddr_wrlvl_cntl_3)  in fsl_ddr_set_memctl_regs()
144 		out_be32(&ddr->ddr_wrlvl_cntl_3, regs->ddr_wrlvl_cntl_3);  in fsl_ddr_set_memctl_regs()
147 	out_be32(&ddr->ddr_sr_cntr, regs->ddr_sr_cntr);  in fsl_ddr_set_memctl_regs()
148 	out_be32(&ddr->ddr_sdram_rcw_1, regs->ddr_sdram_rcw_1);  in fsl_ddr_set_memctl_regs()
149 	out_be32(&ddr->ddr_sdram_rcw_2, regs->ddr_sdram_rcw_2);  in fsl_ddr_set_memctl_regs()
150 	out_be32(&ddr->ddr_cdr1, regs->ddr_cdr1);  in fsl_ddr_set_memctl_regs()
154 			 regs->ddr_sdram_cfg_2 & ~SDRAM_CFG2_D_INIT);  in fsl_ddr_set_memctl_regs()
160 			 regs->ddr_cdr2 & ~DDR_CDR2_VREF_TRAIN_EN);  in fsl_ddr_set_memctl_regs()
164 		out_be32(&ddr->sdram_cfg_2, regs->ddr_sdram_cfg_2);  in fsl_ddr_set_memctl_regs()
165 		out_be32(&ddr->init_addr, regs->ddr_init_addr);  in fsl_ddr_set_memctl_regs()
166 		out_be32(&ddr->init_ext_addr, regs->ddr_init_ext_addr);  in fsl_ddr_set_memctl_regs()
167 		out_be32(&ddr->ddr_cdr2, regs->ddr_cdr2);  in fsl_ddr_set_memctl_regs()
169 	out_be32(&ddr->err_disable, regs->err_disable);  in fsl_ddr_set_memctl_regs()
170 	out_be32(&ddr->err_int_en, regs->err_int_en);  in fsl_ddr_set_memctl_regs()
172 		if (regs->debug[i]) {  in fsl_ddr_set_memctl_regs()
173 			debug("Write to debug_%d as %08x\n", i+1, regs->debug[i]);  in fsl_ddr_set_memctl_regs()
174 			out_be32(&ddr->debug[i], regs->debug[i]);  in fsl_ddr_set_memctl_regs()
198 	temp_sdram_cfg = regs->ddr_sdram_cfg;  in fsl_ddr_set_memctl_regs()
203 	if (regs->ddr_sdram_rcw_2 & 0x00f00000) {  in fsl_ddr_set_memctl_regs()
204 		out_be32(&ddr->timing_cfg_2, regs->timing_cfg_2 & 0xf07fffff);  in fsl_ddr_set_memctl_regs()
206 		out_be32(&ddr->ddr_zq_cntl, regs->ddr_zq_cntl & 0x7fffffff);  in fsl_ddr_set_memctl_regs()
207 		out_be32(&ddr->ddr_wrlvl_cntl, regs->ddr_wrlvl_cntl & 0x7fffffff);  in fsl_ddr_set_memctl_regs()
208 		out_be32(&ddr->sdram_cfg_2, regs->ddr_sdram_cfg_2 & 0xffffffeb);  in fsl_ddr_set_memctl_regs()
214 		out_be32(&ddr->sdram_interval, regs->ddr_sdram_interval & 0xffff);  in fsl_ddr_set_memctl_regs()
221 		switch (regs->ddr_sdram_rcw_2 & 0x00f00000) {  in fsl_ddr_set_memctl_regs()
230 			if (!(regs->cs[2].config & SDRAM_CS_CONFIG_EN))  in fsl_ddr_set_memctl_regs()
250 			if (!(regs->cs[2].config & SDRAM_CS_CONFIG_EN))  in fsl_ddr_set_memctl_regs()
270 			if (!(regs->cs[2].config & SDRAM_CS_CONFIG_EN))  in fsl_ddr_set_memctl_regs()
290 			if (!(regs->cs[2].config & SDRAM_CS_CONFIG_EN))  in fsl_ddr_set_memctl_regs()
310 			if (!(regs->cs[2].config & SDRAM_CS_CONFIG_EN))  in fsl_ddr_set_memctl_regs()
329 		out_be32(&ddr->timing_cfg_2, regs->timing_cfg_2);  in fsl_ddr_set_memctl_regs()
331 		out_be32(&ddr->ddr_zq_cntl, regs->ddr_zq_cntl);  in fsl_ddr_set_memctl_regs()
332 		out_be32(&ddr->ddr_wrlvl_cntl, regs->ddr_wrlvl_cntl);  in fsl_ddr_set_memctl_regs()
333 		out_be32(&ddr->sdram_cfg_2, regs->ddr_sdram_cfg_2);  in fsl_ddr_set_memctl_regs()
336 		out_be32(&ddr->sdram_interval, regs->ddr_sdram_interval);  in fsl_ddr_set_memctl_regs()
401 		if (!(regs->cs[i].config & 0x80000000))  in fsl_ddr_set_memctl_regs()
404 			((regs->cs[i].config >> 14) & 0x3) + 2 +  in fsl_ddr_set_memctl_regs()
405 			((regs->cs[i].config >> 8) & 0x7) + 12 +  in fsl_ddr_set_memctl_regs()
406 			((regs->cs[i].config >> 0) & 0x7) + 8 +  in fsl_ddr_set_memctl_regs()
407 			3 - ((regs->ddr_sdram_cfg >> 19) & 0x3) -  in fsl_ddr_set_memctl_regs()
412 	else if (regs->cs[0].config & 0x20000000) /* 2-way interleaving */  in fsl_ddr_set_memctl_regs()
486 		regs->ddr_sdram_cfg_2 & SDRAM_CFG2_ODT_CFG_MASK);  in fsl_ddr_set_memctl_regs()
504 		regs->ddr_sdram_cfg_2 & SDRAM_CFG2_D_INIT);  in fsl_ddr_set_memctl_regs()
524 		csn_bnds_t = (unsigned int *) &regs->cs[csn].bnds;  in fsl_ddr_set_memctl_regs()
527 			csn, regs->cs[csn].bnds);  in fsl_ddr_set_memctl_regs()
531 			out_be32(&ddr->cs0_bnds, regs->cs[csn].bnds);  in fsl_ddr_set_memctl_regs()
534 			out_be32(&ddr->cs1_bnds, regs->cs[csn].bnds);  in fsl_ddr_set_memctl_regs()
538 			out_be32(&ddr->cs2_bnds, regs->cs[csn].bnds);  in fsl_ddr_set_memctl_regs()
541 			out_be32(&ddr->cs3_bnds, regs->cs[csn].bnds);  in fsl_ddr_set_memctl_regs()